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2cb9c461b4
Summary: To make this work for both AFGR64 and FGR64 register sets, I've had to make the instruction definition consistent with the white lie (that it reads the lower 32-bits of the register) when they are generated by expandBuildPairF64(). Corrected the definition of hasMips32r2() and hasMips64r2() to include MIPS32r6 and MIPS64r6. Depends on D3956 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3957 llvm-svn: 210771
35 lines
874 B
LLVM
35 lines
874 B
LLVM
; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefix=FP32 -check-prefix=CHECK
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; RUN: llc -march=mips < %s | FileCheck %s -check-prefix=FP32 -check-prefix=CHECK
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; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+fp64 < %s | FileCheck %s -check-prefix=FP64 -check-prefix=CHECK
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; RUN: llc -march=mips -mcpu=mips32r2 -mattr=+fp64 < %s | FileCheck %s -check-prefix=FP64 -check-prefix=CHECK
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@a = external global i32
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; CHECK-LABEL: f:
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; FP32: mtc1
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; FP32: mtc1
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; FP64-DAG: mtc1
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; FP64-DAG: mthc1
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define double @f(i32 %a1, double %d) nounwind {
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entry:
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store i32 %a1, i32* @a, align 4
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%add = fadd double %d, 2.000000e+00
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ret double %add
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}
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; CHECK-LABEL: f3:
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; FP32: mfc1
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; FP32: mfc1
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; FP64-DAG: mfc1
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; FP64-DAG: mfhc1
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define void @f3(double %d, i32 %a1) nounwind {
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entry:
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tail call void @f2(i32 %a1, double %d) nounwind
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ret void
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}
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declare void @f2(i32, double)
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