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https://github.com/RPCS3/llvm-mirror.git
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72e0542f2c
When setting the frame pointer, the offset from SP is calculated based on the stack slot it gets allocated, but this slot is in turn based on the order of the CSR list so that list should match the order we actually save the registers in. Mostly it did, but in the edge-case of MachO AAPCS targets it was wrong. llvm-svn: 269459
310 lines
13 KiB
TableGen
310 lines
13 KiB
TableGen
//===-- ARMCallingConv.td - Calling Conventions for ARM ----*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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// This describes the calling conventions for ARM architecture.
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//===----------------------------------------------------------------------===//
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/// CCIfAlign - Match of the original alignment of the arg
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class CCIfAlign<string Align, CCAction A>:
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CCIf<!strconcat("ArgFlags.getOrigAlign() == ", Align), A>;
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//===----------------------------------------------------------------------===//
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// ARM APCS Calling Convention
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//===----------------------------------------------------------------------===//
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def CC_ARM_APCS : CallingConv<[
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// Handles byval parameters.
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CCIfByVal<CCPassByVal<4, 4>>,
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CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
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// Pass SwiftSelf in a callee saved register.
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CCIfSwiftSelf<CCIfType<[i32], CCAssignToReg<[R10]>>>,
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// A SwiftError is passed in R6.
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CCIfSwiftError<CCIfType<[i32], CCAssignToReg<[R6]>>>,
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// Handle all vector types as either f64 or v2f64.
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CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
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CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
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// f64 and v2f64 are passed in adjacent GPRs, possibly split onto the stack
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CCIfType<[f64, v2f64], CCCustom<"CC_ARM_APCS_Custom_f64">>,
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CCIfType<[f32], CCBitConvertToType<i32>>,
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CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>,
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CCIfType<[i32], CCAssignToStack<4, 4>>,
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CCIfType<[f64], CCAssignToStack<8, 4>>,
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CCIfType<[v2f64], CCAssignToStack<16, 4>>
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]>;
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def RetCC_ARM_APCS : CallingConv<[
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CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
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CCIfType<[f32], CCBitConvertToType<i32>>,
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// Pass SwiftSelf in a callee saved register.
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CCIfSwiftSelf<CCIfType<[i32], CCAssignToReg<[R10]>>>,
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// A SwiftError is returned in R6.
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CCIfSwiftError<CCIfType<[i32], CCAssignToReg<[R6]>>>,
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// Handle all vector types as either f64 or v2f64.
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CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
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CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
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CCIfType<[f64, v2f64], CCCustom<"RetCC_ARM_APCS_Custom_f64">>,
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CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>,
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CCIfType<[i64], CCAssignToRegWithShadow<[R0, R2], [R1, R3]>>
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]>;
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//===----------------------------------------------------------------------===//
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// ARM APCS Calling Convention for FastCC (when VFP2 or later is available)
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//===----------------------------------------------------------------------===//
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def FastCC_ARM_APCS : CallingConv<[
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// Handle all vector types as either f64 or v2f64.
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CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
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CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
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CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,
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CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>,
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CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7, S8,
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S9, S10, S11, S12, S13, S14, S15]>>,
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// CPRCs may be allocated to co-processor registers or the stack - they
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// may never be allocated to core registers.
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CCIfType<[f32], CCAssignToStackWithShadow<4, 4, [Q0, Q1, Q2, Q3]>>,
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CCIfType<[f64], CCAssignToStackWithShadow<8, 4, [Q0, Q1, Q2, Q3]>>,
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CCIfType<[v2f64], CCAssignToStackWithShadow<16, 4, [Q0, Q1, Q2, Q3]>>,
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CCDelegateTo<CC_ARM_APCS>
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]>;
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def RetFastCC_ARM_APCS : CallingConv<[
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// Handle all vector types as either f64 or v2f64.
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CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
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CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
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CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,
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CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>,
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CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7, S8,
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S9, S10, S11, S12, S13, S14, S15]>>,
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CCDelegateTo<RetCC_ARM_APCS>
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]>;
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//===----------------------------------------------------------------------===//
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// ARM APCS Calling Convention for GHC
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//===----------------------------------------------------------------------===//
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def CC_ARM_APCS_GHC : CallingConv<[
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// Handle all vector types as either f64 or v2f64.
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CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
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CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
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CCIfType<[v2f64], CCAssignToReg<[Q4, Q5]>>,
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CCIfType<[f64], CCAssignToReg<[D8, D9, D10, D11]>>,
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CCIfType<[f32], CCAssignToReg<[S16, S17, S18, S19, S20, S21, S22, S23]>>,
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// Promote i8/i16 arguments to i32.
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CCIfType<[i8, i16], CCPromoteToType<i32>>,
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// Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, SpLim
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CCIfType<[i32], CCAssignToReg<[R4, R5, R6, R7, R8, R9, R10, R11]>>
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]>;
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//===----------------------------------------------------------------------===//
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// ARM AAPCS (EABI) Calling Convention, common parts
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//===----------------------------------------------------------------------===//
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def CC_ARM_AAPCS_Common : CallingConv<[
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CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
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// i64/f64 is passed in even pairs of GPRs
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// i64 is 8-aligned i32 here, so we may need to eat R1 as a pad register
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// (and the same is true for f64 if VFP is not enabled)
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CCIfType<[i32], CCIfAlign<"8", CCAssignToRegWithShadow<[R0, R2], [R0, R1]>>>,
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CCIfType<[i32], CCIf<"ArgFlags.getOrigAlign() != 8",
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CCAssignToReg<[R0, R1, R2, R3]>>>,
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CCIfType<[i32], CCIfAlign<"8", CCAssignToStackWithShadow<4, 8, [R0, R1, R2, R3]>>>,
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CCIfType<[i32], CCAssignToStackWithShadow<4, 4, [R0, R1, R2, R3]>>,
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CCIfType<[f32], CCAssignToStackWithShadow<4, 4, [Q0, Q1, Q2, Q3]>>,
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CCIfType<[f64], CCAssignToStackWithShadow<8, 8, [Q0, Q1, Q2, Q3]>>,
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CCIfType<[v2f64], CCIfAlign<"16",
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CCAssignToStackWithShadow<16, 16, [Q0, Q1, Q2, Q3]>>>,
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CCIfType<[v2f64], CCAssignToStackWithShadow<16, 8, [Q0, Q1, Q2, Q3]>>
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]>;
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def RetCC_ARM_AAPCS_Common : CallingConv<[
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CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
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CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>,
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CCIfType<[i64], CCAssignToRegWithShadow<[R0, R2], [R1, R3]>>
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]>;
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//===----------------------------------------------------------------------===//
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// ARM AAPCS (EABI) Calling Convention
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//===----------------------------------------------------------------------===//
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def CC_ARM_AAPCS : CallingConv<[
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// Handles byval parameters.
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CCIfByVal<CCPassByVal<4, 4>>,
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// The 'nest' parameter, if any, is passed in R12.
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CCIfNest<CCAssignToReg<[R12]>>,
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// Handle all vector types as either f64 or v2f64.
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CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
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CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
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// Pass SwiftSelf in a callee saved register.
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CCIfSwiftSelf<CCIfType<[i32], CCAssignToReg<[R10]>>>,
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// A SwiftError is passed in R6.
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CCIfSwiftError<CCIfType<[i32], CCAssignToReg<[R6]>>>,
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CCIfType<[f64, v2f64], CCCustom<"CC_ARM_AAPCS_Custom_f64">>,
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CCIfType<[f32], CCBitConvertToType<i32>>,
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CCDelegateTo<CC_ARM_AAPCS_Common>
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]>;
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def RetCC_ARM_AAPCS : CallingConv<[
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// Handle all vector types as either f64 or v2f64.
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CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
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CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
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// Pass SwiftSelf in a callee saved register.
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CCIfSwiftSelf<CCIfType<[i32], CCAssignToReg<[R10]>>>,
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// A SwiftError is returned in R6.
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CCIfSwiftError<CCIfType<[i32], CCAssignToReg<[R6]>>>,
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CCIfType<[f64, v2f64], CCCustom<"RetCC_ARM_AAPCS_Custom_f64">>,
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CCIfType<[f32], CCBitConvertToType<i32>>,
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CCDelegateTo<RetCC_ARM_AAPCS_Common>
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]>;
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//===----------------------------------------------------------------------===//
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// ARM AAPCS-VFP (EABI) Calling Convention
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// Also used for FastCC (when VFP2 or later is available)
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//===----------------------------------------------------------------------===//
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def CC_ARM_AAPCS_VFP : CallingConv<[
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// Handles byval parameters.
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CCIfByVal<CCPassByVal<4, 4>>,
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// Handle all vector types as either f64 or v2f64.
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CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
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CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
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// Pass SwiftSelf in a callee saved register.
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CCIfSwiftSelf<CCIfType<[i32], CCAssignToReg<[R10]>>>,
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// A SwiftError is passed in R6.
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CCIfSwiftError<CCIfType<[i32], CCAssignToReg<[R6]>>>,
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// HFAs are passed in a contiguous block of registers, or on the stack
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CCIfConsecutiveRegs<CCCustom<"CC_ARM_AAPCS_Custom_Aggregate">>,
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CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,
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CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>,
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CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7, S8,
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S9, S10, S11, S12, S13, S14, S15]>>,
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CCDelegateTo<CC_ARM_AAPCS_Common>
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]>;
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def RetCC_ARM_AAPCS_VFP : CallingConv<[
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// Handle all vector types as either f64 or v2f64.
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CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
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CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
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// Pass SwiftSelf in a callee saved register.
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CCIfSwiftSelf<CCIfType<[i32], CCAssignToReg<[R10]>>>,
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// A SwiftError is returned in R6.
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CCIfSwiftError<CCIfType<[i32], CCAssignToReg<[R6]>>>,
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CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,
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CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>,
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CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7, S8,
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S9, S10, S11, S12, S13, S14, S15]>>,
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CCDelegateTo<RetCC_ARM_AAPCS_Common>
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]>;
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//===----------------------------------------------------------------------===//
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// Callee-saved register lists.
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//===----------------------------------------------------------------------===//
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def CSR_NoRegs : CalleeSavedRegs<(add)>;
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def CSR_AAPCS : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6, R5, R4,
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(sequence "D%u", 15, 8))>;
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// The order of callee-saved registers needs to match the order we actually push
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// them in FrameLowering, because this order is what's used by
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// PrologEpilogInserter to allocate frame index slots. So when R7 is the frame
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// pointer, we use this AAPCS alternative.
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def CSR_AAPCS_SplitPush : CalleeSavedRegs<(add LR, R7, R6, R5, R4,
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R11, R10, R9, R8,
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(sequence "D%u", 15, 8))>;
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// Constructors and destructors return 'this' in the ARM C++ ABI; since 'this'
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// and the pointer return value are both passed in R0 in these cases, this can
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// be partially modelled by treating R0 as a callee-saved register
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// Only the resulting RegMask is used; the SaveList is ignored
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def CSR_AAPCS_ThisReturn : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6,
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R5, R4, (sequence "D%u", 15, 8),
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R0)>;
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// iOS ABI deviates from ARM standard ABI. R9 is not a callee-saved register.
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// Also save R7-R4 first to match the stack frame fixed spill areas.
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def CSR_iOS : CalleeSavedRegs<(add LR, R7, R6, R5, R4, (sub CSR_AAPCS, R9))>;
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// R6 is used to pass swifterror, remove it from CSR.
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def CSR_iOS_SwiftError : CalleeSavedRegs<(sub CSR_iOS, R6)>;
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def CSR_iOS_ThisReturn : CalleeSavedRegs<(add LR, R7, R6, R5, R4,
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(sub CSR_AAPCS_ThisReturn, R9))>;
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def CSR_iOS_TLSCall : CalleeSavedRegs<(add LR, SP,
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(sequence "R%u", 12, 1),
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(sequence "D%u", 31, 0))>;
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// C++ TLS access function saves all registers except SP. Try to match
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// the order of CSRs in CSR_iOS.
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def CSR_iOS_CXX_TLS : CalleeSavedRegs<(add CSR_iOS, (sequence "R%u", 12, 1),
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(sequence "D%u", 31, 0))>;
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// CSRs that are handled by prologue, epilogue.
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def CSR_iOS_CXX_TLS_PE : CalleeSavedRegs<(add LR, R12, R11, R7, R5, R4)>;
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// CSRs that are handled explicitly via copies.
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def CSR_iOS_CXX_TLS_ViaCopy : CalleeSavedRegs<(sub CSR_iOS_CXX_TLS,
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CSR_iOS_CXX_TLS_PE)>;
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// The "interrupt" attribute is used to generate code that is acceptable in
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// exception-handlers of various kinds. It makes us use a different return
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// instruction (handled elsewhere) and affects which registers we must return to
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// our "caller" in the same state as we receive them.
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// For most interrupts, all registers except SP and LR are shared with
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// user-space. We mark LR to be saved anyway, since this is what the ARM backend
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// generally does rather than tracking its liveness as a normal register.
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def CSR_GenericInt : CalleeSavedRegs<(add LR, (sequence "R%u", 12, 0))>;
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// The fast interrupt handlers have more private state and get their own copies
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// of R8-R12, in addition to SP and LR. As before, mark LR for saving too.
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// FIXME: we mark R11 as callee-saved since it's often the frame-pointer, and
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// current frame lowering expects to encounter it while processing callee-saved
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// registers.
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def CSR_FIQ : CalleeSavedRegs<(add LR, R11, (sequence "R%u", 7, 0))>;
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