Tim Northover 86fa0255b2 AArch64: TableGenerate system instruction operands. ... The way the named arguments for various system instructions are handled at the moment has a few problems: - Large-scale duplication between AArch64BaseInfo.h and AArch64BaseInfo.cpp - That weird Mapping class that I have no idea what I was on when I thought it was a good idea. - Searches are performed linearly through the entire list. - We print absolutely all registers in upper-case, even though some are canonically mixed case (SPSel for example). - The ARM ARM specifies sysregs in terms of 5 fields, but those are relegated to comments in our implementation, with a slightly opaque hex value indicating the canonical encoding LLVM will use. This adds a new TableGen backend to produce efficiently searchable tables, and switches AArch64 over to using that infrastructure. llvm-svn: 274576		2016-07-05 21:23:04 +00:00
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AArch64InstPrinter.cpp	AArch64: TableGenerate system instruction operands.	2016-07-05 21:23:04 +00:00
AArch64InstPrinter.h
CMakeLists.txt
LLVMBuild.txt