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286 lines
6.9 KiB
TableGen
286 lines
6.9 KiB
TableGen
//===-- SIInstrFormats.td - SI Instruction Encodings ----------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// SI Instruction format definitions.
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//
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//===----------------------------------------------------------------------===//
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class InstSI <dag outs, dag ins, string asm = "",
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list<dag> pattern = []> :
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AMDGPUInst<outs, ins, asm, pattern>, PredicateControl {
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// Low bits - basic encoding information.
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field bit SALU = 0;
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field bit VALU = 0;
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// SALU instruction formats.
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field bit SOP1 = 0;
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field bit SOP2 = 0;
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field bit SOPC = 0;
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field bit SOPK = 0;
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field bit SOPP = 0;
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// VALU instruction formats.
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field bit VOP1 = 0;
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field bit VOP2 = 0;
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field bit VOPC = 0;
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field bit VOP3 = 0;
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field bit VINTRP = 0;
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field bit SDWA = 0;
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field bit DPP = 0;
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// Memory instruction formats.
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field bit MUBUF = 0;
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field bit MTBUF = 0;
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field bit SMRD = 0;
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field bit MIMG = 0;
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field bit EXP = 0;
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field bit FLAT = 0;
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field bit DS = 0;
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// Pseudo instruction formats.
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field bit VGPRSpill = 0;
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field bit SGPRSpill = 0;
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// High bits - other information.
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field bit VM_CNT = 0;
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field bit EXP_CNT = 0;
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field bit LGKM_CNT = 0;
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// Whether WQM _must_ be enabled for this instruction.
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field bit WQM = 0;
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// Whether WQM _must_ be disabled for this instruction.
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field bit DisableWQM = 0;
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field bit Gather4 = 0;
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// Most sopk treat the immediate as a signed 16-bit, however some
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// use it as unsigned.
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field bit SOPKZext = 0;
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// This is an s_store_dword* instruction that requires a cache flush
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// on wave termination. It is necessary to distinguish from mayStore
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// SMEM instructions like the cache flush ones.
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field bit ScalarStore = 0;
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// Whether the operands can be ignored when computing the
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// instruction size.
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field bit FixedSize = 0;
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// This bit tells the assembler to use the 32-bit encoding in case it
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// is unable to infer the encoding from the operands.
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field bit VOPAsmPrefer32Bit = 0;
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// These need to be kept in sync with the enum in SIInstrFlags.
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let TSFlags{0} = SALU;
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let TSFlags{1} = VALU;
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let TSFlags{2} = SOP1;
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let TSFlags{3} = SOP2;
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let TSFlags{4} = SOPC;
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let TSFlags{5} = SOPK;
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let TSFlags{6} = SOPP;
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let TSFlags{7} = VOP1;
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let TSFlags{8} = VOP2;
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let TSFlags{9} = VOPC;
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let TSFlags{10} = VOP3;
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let TSFlags{13} = VINTRP;
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let TSFlags{14} = SDWA;
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let TSFlags{15} = DPP;
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let TSFlags{16} = MUBUF;
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let TSFlags{17} = MTBUF;
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let TSFlags{18} = SMRD;
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let TSFlags{19} = MIMG;
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let TSFlags{20} = EXP;
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let TSFlags{21} = FLAT;
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let TSFlags{22} = DS;
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let TSFlags{23} = VGPRSpill;
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let TSFlags{24} = SGPRSpill;
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let TSFlags{32} = VM_CNT;
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let TSFlags{33} = EXP_CNT;
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let TSFlags{34} = LGKM_CNT;
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let TSFlags{35} = WQM;
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let TSFlags{36} = DisableWQM;
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let TSFlags{37} = Gather4;
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let TSFlags{38} = SOPKZext;
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let TSFlags{39} = ScalarStore;
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let TSFlags{40} = FixedSize;
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let TSFlags{41} = VOPAsmPrefer32Bit;
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let SchedRW = [Write32Bit];
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field bits<1> DisableSIDecoder = 0;
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field bits<1> DisableVIDecoder = 0;
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field bits<1> DisableDecoder = 0;
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let isAsmParserOnly = !if(!eq(DisableDecoder{0}, {0}), 0, 1);
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let AsmVariantName = AMDGPUAsmVariants.Default;
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}
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class PseudoInstSI<dag outs, dag ins, list<dag> pattern = []>
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: InstSI<outs, ins, "", pattern> {
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let isPseudo = 1;
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let isCodeGenOnly = 1;
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}
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class SPseudoInstSI<dag outs, dag ins, list<dag> pattern = []>
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: PseudoInstSI<outs, ins, pattern> {
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let SALU = 1;
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}
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class VPseudoInstSI<dag outs, dag ins, list<dag> pattern = []>
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: PseudoInstSI<outs, ins, pattern> {
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let VALU = 1;
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let Uses = [EXEC];
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}
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class CFPseudoInstSI<dag outs, dag ins, list<dag> pattern = [],
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bit UseExec = 0, bit DefExec = 0> :
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SPseudoInstSI<outs, ins, pattern> {
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let Uses = !if(UseExec, [EXEC], []);
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let Defs = !if(DefExec, [EXEC, SCC], [SCC]);
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let mayLoad = 0;
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let mayStore = 0;
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let hasSideEffects = 0;
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}
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class Enc32 {
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field bits<32> Inst;
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int Size = 4;
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}
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class Enc64 {
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field bits<64> Inst;
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int Size = 8;
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}
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class VOPDstOperand <RegisterClass rc> : RegisterOperand <rc, "printVOPDst">;
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class VINTRPe <bits<2> op> : Enc32 {
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bits<8> vdst;
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bits<8> vsrc;
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bits<2> attrchan;
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bits<6> attr;
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let Inst{7-0} = vsrc;
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let Inst{9-8} = attrchan;
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let Inst{15-10} = attr;
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let Inst{17-16} = op;
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let Inst{25-18} = vdst;
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let Inst{31-26} = 0x32; // encoding
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}
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class MIMGe <bits<7> op> : Enc64 {
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bits<8> vdata;
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bits<4> dmask;
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bits<1> unorm;
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bits<1> glc;
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bits<1> da;
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bits<1> r128;
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bits<1> tfe;
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bits<1> lwe;
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bits<1> slc;
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bits<8> vaddr;
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bits<7> srsrc;
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bits<7> ssamp;
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let Inst{11-8} = dmask;
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let Inst{12} = unorm;
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let Inst{13} = glc;
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let Inst{14} = da;
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let Inst{15} = r128;
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let Inst{16} = tfe;
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let Inst{17} = lwe;
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let Inst{24-18} = op;
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let Inst{25} = slc;
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let Inst{31-26} = 0x3c;
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let Inst{39-32} = vaddr;
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let Inst{47-40} = vdata;
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let Inst{52-48} = srsrc{6-2};
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let Inst{57-53} = ssamp{6-2};
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}
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class EXPe : Enc64 {
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bits<4> en;
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bits<6> tgt;
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bits<1> compr;
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bits<1> done;
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bits<1> vm;
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bits<8> vsrc0;
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bits<8> vsrc1;
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bits<8> vsrc2;
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bits<8> vsrc3;
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let Inst{3-0} = en;
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let Inst{9-4} = tgt;
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let Inst{10} = compr;
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let Inst{11} = done;
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let Inst{12} = vm;
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let Inst{31-26} = 0x3e;
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let Inst{39-32} = vsrc0;
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let Inst{47-40} = vsrc1;
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let Inst{55-48} = vsrc2;
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let Inst{63-56} = vsrc3;
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}
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let Uses = [EXEC] in {
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class VINTRPCommon <dag outs, dag ins, string asm, list<dag> pattern> :
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InstSI <outs, ins, asm, pattern> {
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let VINTRP = 1;
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// VINTRP instructions read parameter values from LDS, but these parameter
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// values are stored outside of the LDS memory that is allocated to the
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// shader for general purpose use.
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//
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// While it may be possible for ds_read/ds_write instructions to access
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// the parameter values in LDS, this would essentially be an out-of-bounds
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// memory access which we consider to be undefined behavior.
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//
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// So even though these instructions read memory, this memory is outside the
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// addressable memory space for the shader, and we consider these instructions
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// to be readnone.
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let mayLoad = 0;
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let mayStore = 0;
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let hasSideEffects = 0;
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}
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class EXPCommon<dag outs, dag ins, string asm, list<dag> pattern> :
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InstSI<outs, ins, asm, pattern> {
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let EXP = 1;
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let EXP_CNT = 1;
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let mayLoad = 0; // Set to 1 if done bit is set.
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let mayStore = 1;
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let UseNamedOperandTable = 1;
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let Uses = [EXEC];
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let SchedRW = [WriteExport];
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}
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} // End Uses = [EXEC]
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class MIMG <dag outs, dag ins, string asm, list<dag> pattern> :
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InstSI <outs, ins, asm, pattern> {
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let VM_CNT = 1;
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let EXP_CNT = 1;
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let MIMG = 1;
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let Uses = [EXEC];
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let UseNamedOperandTable = 1;
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let hasSideEffects = 0; // XXX ????
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}
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