1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-31 16:02:52 +01:00
llvm-mirror/test/CodeGen/ARM/mul_const.ll
Jim Grosbach d2cf0742a4 Update tests to handle MC-inst instruction printing of shift operations. The
legacy asm printer uses instructions of the form, "mov r0, r0, lsl #3", while
the MC-instruction printer uses the form "lsl r0, r0, #3". The latter mnemonic
is correct and preferred according the ARM documentation (A8.6.98). The former
are pseudo-instructions for the latter.

llvm-svn: 114221
2010-09-17 21:58:46 +00:00

44 lines
769 B
LLVM

; RUN: llc < %s -march=arm | FileCheck %s
define i32 @t9(i32 %v) nounwind readnone {
entry:
; CHECK: t9:
; CHECK: add r0, r0, r0, lsl #3
%0 = mul i32 %v, 9
ret i32 %0
}
define i32 @t7(i32 %v) nounwind readnone {
entry:
; CHECK: t7:
; CHECK: rsb r0, r0, r0, lsl #3
%0 = mul i32 %v, 7
ret i32 %0
}
define i32 @t5(i32 %v) nounwind readnone {
entry:
; CHECK: t5:
; CHECK: add r0, r0, r0, lsl #2
%0 = mul i32 %v, 5
ret i32 %0
}
define i32 @t3(i32 %v) nounwind readnone {
entry:
; CHECK: t3:
; CHECK: add r0, r0, r0, lsl #1
%0 = mul i32 %v, 3
ret i32 %0
}
define i32 @t12288(i32 %v) nounwind readnone {
entry:
; CHECK: t12288:
; CHECK: add r0, r0, r0, lsl #1
; CHECK: lsl{{.*}}#12
%0 = mul i32 %v, 12288
ret i32 %0
}