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llvm-mirror/test/CodeGen/Generic/add-with-overflow-128.ll
Andrew Trick cc701bcfdc Fixes PR8823: add-with-overflow-128.ll
In the bottom-up selection DAG scheduling, handle two-address
instructions that read/write unspillable registers. Treat
the entire chain of two-address nodes as a single live range.

llvm-svn: 122472
2010-12-23 03:15:51 +00:00

35 lines
1.0 KiB
LLVM

; RUN: llc < %s
@ok = internal constant [4 x i8] c"%d\0A\00"
@no = internal constant [4 x i8] c"no\0A\00"
define i1 @func2(i128 zeroext %v1, i128 zeroext %v2) nounwind {
entry:
%t = call {i128, i1} @llvm.uadd.with.overflow.i128(i128 %v1, i128 %v2)
%sum = extractvalue {i128, i1} %t, 0
%sum32 = trunc i128 %sum to i32
%obit = extractvalue {i128, i1} %t, 1
br i1 %obit, label %carry, label %normal
normal:
%t1 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @ok, i32 0, i32 0), i32 %sum32 ) nounwind
ret i1 true
carry:
%t2 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @no, i32 0, i32 0) ) nounwind
ret i1 false
}
declare i32 @printf(i8*, ...) nounwind
declare {i96, i1} @llvm.sadd.with.overflow.i96(i96, i96)
declare {i128, i1} @llvm.uadd.with.overflow.i128(i128, i128)
define i1 @func1(i96 signext %v1, i96 signext %v2) nounwind {
entry:
%t = call {i96, i1} @llvm.sadd.with.overflow.i96(i96 %v1, i96 %v2)
%obit = extractvalue {i96, i1} %t, 1
ret i1 %obit
}