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ace00a09c8
Also change some pointer arguments to references at some places where 0-pointers are not allowed. llvm-svn: 192396
1438 lines
50 KiB
C++
1438 lines
50 KiB
C++
//===---------- SplitKit.cpp - Toolkit for splitting live ranges ----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the SplitAnalysis class as well as mutator functions for
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// live range splitting.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "regalloc"
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#include "SplitKit.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/CodeGen/LiveRangeEdit.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineLoopInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/VirtRegMap.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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using namespace llvm;
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STATISTIC(NumFinished, "Number of splits finished");
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STATISTIC(NumSimple, "Number of splits that were simple");
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STATISTIC(NumCopies, "Number of copies inserted for splitting");
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STATISTIC(NumRemats, "Number of rematerialized defs for splitting");
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STATISTIC(NumRepairs, "Number of invalid live ranges repaired");
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//===----------------------------------------------------------------------===//
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// Split Analysis
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//===----------------------------------------------------------------------===//
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SplitAnalysis::SplitAnalysis(const VirtRegMap &vrm,
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const LiveIntervals &lis,
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const MachineLoopInfo &mli)
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: MF(vrm.getMachineFunction()),
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VRM(vrm),
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LIS(lis),
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Loops(mli),
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TII(*MF.getTarget().getInstrInfo()),
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CurLI(0),
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LastSplitPoint(MF.getNumBlockIDs()) {}
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void SplitAnalysis::clear() {
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UseSlots.clear();
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UseBlocks.clear();
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ThroughBlocks.clear();
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CurLI = 0;
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DidRepairRange = false;
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}
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SlotIndex SplitAnalysis::computeLastSplitPoint(unsigned Num) {
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const MachineBasicBlock *MBB = MF.getBlockNumbered(Num);
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const MachineBasicBlock *LPad = MBB->getLandingPadSuccessor();
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std::pair<SlotIndex, SlotIndex> &LSP = LastSplitPoint[Num];
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SlotIndex MBBEnd = LIS.getMBBEndIdx(MBB);
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// Compute split points on the first call. The pair is independent of the
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// current live interval.
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if (!LSP.first.isValid()) {
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MachineBasicBlock::const_iterator FirstTerm = MBB->getFirstTerminator();
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if (FirstTerm == MBB->end())
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LSP.first = MBBEnd;
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else
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LSP.first = LIS.getInstructionIndex(FirstTerm);
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// If there is a landing pad successor, also find the call instruction.
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if (!LPad)
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return LSP.first;
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// There may not be a call instruction (?) in which case we ignore LPad.
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LSP.second = LSP.first;
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for (MachineBasicBlock::const_iterator I = MBB->end(), E = MBB->begin();
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I != E;) {
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--I;
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if (I->isCall()) {
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LSP.second = LIS.getInstructionIndex(I);
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break;
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}
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}
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}
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// If CurLI is live into a landing pad successor, move the last split point
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// back to the call that may throw.
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if (!LPad || !LSP.second || !LIS.isLiveInToMBB(*CurLI, LPad))
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return LSP.first;
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// Find the value leaving MBB.
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const VNInfo *VNI = CurLI->getVNInfoBefore(MBBEnd);
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if (!VNI)
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return LSP.first;
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// If the value leaving MBB was defined after the call in MBB, it can't
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// really be live-in to the landing pad. This can happen if the landing pad
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// has a PHI, and this register is undef on the exceptional edge.
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// <rdar://problem/10664933>
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if (!SlotIndex::isEarlierInstr(VNI->def, LSP.second) && VNI->def < MBBEnd)
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return LSP.first;
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// Value is properly live-in to the landing pad.
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// Only allow splits before the call.
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return LSP.second;
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}
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MachineBasicBlock::iterator
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SplitAnalysis::getLastSplitPointIter(MachineBasicBlock *MBB) {
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SlotIndex LSP = getLastSplitPoint(MBB->getNumber());
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if (LSP == LIS.getMBBEndIdx(MBB))
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return MBB->end();
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return LIS.getInstructionFromIndex(LSP);
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}
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/// analyzeUses - Count instructions, basic blocks, and loops using CurLI.
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void SplitAnalysis::analyzeUses() {
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assert(UseSlots.empty() && "Call clear first");
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// First get all the defs from the interval values. This provides the correct
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// slots for early clobbers.
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for (LiveInterval::const_vni_iterator I = CurLI->vni_begin(),
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E = CurLI->vni_end(); I != E; ++I)
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if (!(*I)->isPHIDef() && !(*I)->isUnused())
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UseSlots.push_back((*I)->def);
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// Get use slots form the use-def chain.
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const MachineRegisterInfo &MRI = MF.getRegInfo();
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for (MachineRegisterInfo::use_nodbg_iterator
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I = MRI.use_nodbg_begin(CurLI->reg), E = MRI.use_nodbg_end(); I != E;
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++I)
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if (!I.getOperand().isUndef())
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UseSlots.push_back(LIS.getInstructionIndex(&*I).getRegSlot());
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array_pod_sort(UseSlots.begin(), UseSlots.end());
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// Remove duplicates, keeping the smaller slot for each instruction.
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// That is what we want for early clobbers.
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UseSlots.erase(std::unique(UseSlots.begin(), UseSlots.end(),
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SlotIndex::isSameInstr),
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UseSlots.end());
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// Compute per-live block info.
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if (!calcLiveBlockInfo()) {
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// FIXME: calcLiveBlockInfo found inconsistencies in the live range.
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// I am looking at you, RegisterCoalescer!
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DidRepairRange = true;
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++NumRepairs;
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DEBUG(dbgs() << "*** Fixing inconsistent live interval! ***\n");
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const_cast<LiveIntervals&>(LIS)
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.shrinkToUses(const_cast<LiveInterval*>(CurLI));
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UseBlocks.clear();
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ThroughBlocks.clear();
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bool fixed = calcLiveBlockInfo();
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(void)fixed;
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assert(fixed && "Couldn't fix broken live interval");
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}
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DEBUG(dbgs() << "Analyze counted "
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<< UseSlots.size() << " instrs in "
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<< UseBlocks.size() << " blocks, through "
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<< NumThroughBlocks << " blocks.\n");
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}
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/// calcLiveBlockInfo - Fill the LiveBlocks array with information about blocks
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/// where CurLI is live.
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bool SplitAnalysis::calcLiveBlockInfo() {
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ThroughBlocks.resize(MF.getNumBlockIDs());
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NumThroughBlocks = NumGapBlocks = 0;
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if (CurLI->empty())
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return true;
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LiveInterval::const_iterator LVI = CurLI->begin();
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LiveInterval::const_iterator LVE = CurLI->end();
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SmallVectorImpl<SlotIndex>::const_iterator UseI, UseE;
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UseI = UseSlots.begin();
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UseE = UseSlots.end();
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// Loop over basic blocks where CurLI is live.
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MachineFunction::iterator MFI = LIS.getMBBFromIndex(LVI->start);
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for (;;) {
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BlockInfo BI;
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BI.MBB = MFI;
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SlotIndex Start, Stop;
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tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(BI.MBB);
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// If the block contains no uses, the range must be live through. At one
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// point, RegisterCoalescer could create dangling ranges that ended
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// mid-block.
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if (UseI == UseE || *UseI >= Stop) {
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++NumThroughBlocks;
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ThroughBlocks.set(BI.MBB->getNumber());
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// The range shouldn't end mid-block if there are no uses. This shouldn't
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// happen.
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if (LVI->end < Stop)
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return false;
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} else {
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// This block has uses. Find the first and last uses in the block.
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BI.FirstInstr = *UseI;
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assert(BI.FirstInstr >= Start);
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do ++UseI;
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while (UseI != UseE && *UseI < Stop);
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BI.LastInstr = UseI[-1];
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assert(BI.LastInstr < Stop);
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// LVI is the first live segment overlapping MBB.
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BI.LiveIn = LVI->start <= Start;
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// When not live in, the first use should be a def.
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if (!BI.LiveIn) {
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assert(LVI->start == LVI->valno->def && "Dangling Segment start");
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assert(LVI->start == BI.FirstInstr && "First instr should be a def");
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BI.FirstDef = BI.FirstInstr;
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}
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// Look for gaps in the live range.
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BI.LiveOut = true;
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while (LVI->end < Stop) {
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SlotIndex LastStop = LVI->end;
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if (++LVI == LVE || LVI->start >= Stop) {
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BI.LiveOut = false;
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BI.LastInstr = LastStop;
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break;
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}
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if (LastStop < LVI->start) {
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// There is a gap in the live range. Create duplicate entries for the
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// live-in snippet and the live-out snippet.
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++NumGapBlocks;
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// Push the Live-in part.
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BI.LiveOut = false;
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UseBlocks.push_back(BI);
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UseBlocks.back().LastInstr = LastStop;
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// Set up BI for the live-out part.
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BI.LiveIn = false;
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BI.LiveOut = true;
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BI.FirstInstr = BI.FirstDef = LVI->start;
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}
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// A Segment that starts in the middle of the block must be a def.
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assert(LVI->start == LVI->valno->def && "Dangling Segment start");
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if (!BI.FirstDef)
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BI.FirstDef = LVI->start;
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}
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UseBlocks.push_back(BI);
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// LVI is now at LVE or LVI->end >= Stop.
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if (LVI == LVE)
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break;
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}
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// Live segment ends exactly at Stop. Move to the next segment.
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if (LVI->end == Stop && ++LVI == LVE)
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break;
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// Pick the next basic block.
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if (LVI->start < Stop)
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++MFI;
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else
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MFI = LIS.getMBBFromIndex(LVI->start);
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}
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assert(getNumLiveBlocks() == countLiveBlocks(CurLI) && "Bad block count");
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return true;
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}
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unsigned SplitAnalysis::countLiveBlocks(const LiveInterval *cli) const {
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if (cli->empty())
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return 0;
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LiveInterval *li = const_cast<LiveInterval*>(cli);
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LiveInterval::iterator LVI = li->begin();
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LiveInterval::iterator LVE = li->end();
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unsigned Count = 0;
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// Loop over basic blocks where li is live.
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MachineFunction::const_iterator MFI = LIS.getMBBFromIndex(LVI->start);
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SlotIndex Stop = LIS.getMBBEndIdx(MFI);
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for (;;) {
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++Count;
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LVI = li->advanceTo(LVI, Stop);
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if (LVI == LVE)
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return Count;
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do {
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++MFI;
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Stop = LIS.getMBBEndIdx(MFI);
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} while (Stop <= LVI->start);
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}
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}
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bool SplitAnalysis::isOriginalEndpoint(SlotIndex Idx) const {
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unsigned OrigReg = VRM.getOriginal(CurLI->reg);
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const LiveInterval &Orig = LIS.getInterval(OrigReg);
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assert(!Orig.empty() && "Splitting empty interval?");
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LiveInterval::const_iterator I = Orig.find(Idx);
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// Range containing Idx should begin at Idx.
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if (I != Orig.end() && I->start <= Idx)
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return I->start == Idx;
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// Range does not contain Idx, previous must end at Idx.
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return I != Orig.begin() && (--I)->end == Idx;
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}
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void SplitAnalysis::analyze(const LiveInterval *li) {
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clear();
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CurLI = li;
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analyzeUses();
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}
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//===----------------------------------------------------------------------===//
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// Split Editor
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//===----------------------------------------------------------------------===//
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/// Create a new SplitEditor for editing the LiveInterval analyzed by SA.
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SplitEditor::SplitEditor(SplitAnalysis &sa,
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LiveIntervals &lis,
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VirtRegMap &vrm,
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MachineDominatorTree &mdt,
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MachineBlockFrequencyInfo &mbfi)
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: SA(sa), LIS(lis), VRM(vrm),
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MRI(vrm.getMachineFunction().getRegInfo()),
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MDT(mdt),
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TII(*vrm.getMachineFunction().getTarget().getInstrInfo()),
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TRI(*vrm.getMachineFunction().getTarget().getRegisterInfo()),
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MBFI(mbfi),
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Edit(0),
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OpenIdx(0),
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SpillMode(SM_Partition),
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RegAssign(Allocator)
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{}
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void SplitEditor::reset(LiveRangeEdit &LRE, ComplementSpillMode SM) {
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Edit = &LRE;
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SpillMode = SM;
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OpenIdx = 0;
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RegAssign.clear();
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Values.clear();
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// Reset the LiveRangeCalc instances needed for this spill mode.
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LRCalc[0].reset(&VRM.getMachineFunction(), LIS.getSlotIndexes(), &MDT,
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&LIS.getVNInfoAllocator());
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if (SpillMode)
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LRCalc[1].reset(&VRM.getMachineFunction(), LIS.getSlotIndexes(), &MDT,
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&LIS.getVNInfoAllocator());
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// We don't need an AliasAnalysis since we will only be performing
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// cheap-as-a-copy remats anyway.
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Edit->anyRematerializable(0);
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}
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#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
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void SplitEditor::dump() const {
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if (RegAssign.empty()) {
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dbgs() << " empty\n";
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return;
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}
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for (RegAssignMap::const_iterator I = RegAssign.begin(); I.valid(); ++I)
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dbgs() << " [" << I.start() << ';' << I.stop() << "):" << I.value();
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dbgs() << '\n';
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}
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#endif
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VNInfo *SplitEditor::defValue(unsigned RegIdx,
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const VNInfo *ParentVNI,
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SlotIndex Idx) {
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assert(ParentVNI && "Mapping NULL value");
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assert(Idx.isValid() && "Invalid SlotIndex");
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assert(Edit->getParent().getVNInfoAt(Idx) == ParentVNI && "Bad Parent VNI");
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LiveInterval *LI = &LIS.getInterval(Edit->get(RegIdx));
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// Create a new value.
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VNInfo *VNI = LI->getNextValue(Idx, LIS.getVNInfoAllocator());
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// Use insert for lookup, so we can add missing values with a second lookup.
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std::pair<ValueMap::iterator, bool> InsP =
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Values.insert(std::make_pair(std::make_pair(RegIdx, ParentVNI->id),
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ValueForcePair(VNI, false)));
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// This was the first time (RegIdx, ParentVNI) was mapped.
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// Keep it as a simple def without any liveness.
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if (InsP.second)
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return VNI;
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// If the previous value was a simple mapping, add liveness for it now.
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if (VNInfo *OldVNI = InsP.first->second.getPointer()) {
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SlotIndex Def = OldVNI->def;
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LI->addSegment(LiveInterval::Segment(Def, Def.getDeadSlot(), OldVNI));
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// No longer a simple mapping. Switch to a complex, non-forced mapping.
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InsP.first->second = ValueForcePair();
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}
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// This is a complex mapping, add liveness for VNI
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SlotIndex Def = VNI->def;
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LI->addSegment(LiveInterval::Segment(Def, Def.getDeadSlot(), VNI));
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return VNI;
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}
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void SplitEditor::forceRecompute(unsigned RegIdx, const VNInfo *ParentVNI) {
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assert(ParentVNI && "Mapping NULL value");
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ValueForcePair &VFP = Values[std::make_pair(RegIdx, ParentVNI->id)];
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VNInfo *VNI = VFP.getPointer();
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// ParentVNI was either unmapped or already complex mapped. Either way, just
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// set the force bit.
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if (!VNI) {
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VFP.setInt(true);
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return;
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}
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// This was previously a single mapping. Make sure the old def is represented
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// by a trivial live range.
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SlotIndex Def = VNI->def;
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LiveInterval *LI = &LIS.getInterval(Edit->get(RegIdx));
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LI->addSegment(LiveInterval::Segment(Def, Def.getDeadSlot(), VNI));
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// Mark as complex mapped, forced.
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VFP = ValueForcePair(0, true);
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}
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VNInfo *SplitEditor::defFromParent(unsigned RegIdx,
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VNInfo *ParentVNI,
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SlotIndex UseIdx,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) {
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MachineInstr *CopyMI = 0;
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SlotIndex Def;
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LiveInterval *LI = &LIS.getInterval(Edit->get(RegIdx));
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// We may be trying to avoid interference that ends at a deleted instruction,
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// so always begin RegIdx 0 early and all others late.
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bool Late = RegIdx != 0;
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// Attempt cheap-as-a-copy rematerialization.
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LiveRangeEdit::Remat RM(ParentVNI);
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if (Edit->canRematerializeAt(RM, UseIdx, true)) {
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Def = Edit->rematerializeAt(MBB, I, LI->reg, RM, TRI, Late);
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++NumRemats;
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} else {
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// Can't remat, just insert a copy from parent.
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CopyMI = BuildMI(MBB, I, DebugLoc(), TII.get(TargetOpcode::COPY), LI->reg)
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.addReg(Edit->getReg());
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Def = LIS.getSlotIndexes()->insertMachineInstrInMaps(CopyMI, Late)
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.getRegSlot();
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++NumCopies;
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}
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// Define the value in Reg.
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return defValue(RegIdx, ParentVNI, Def);
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}
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/// Create a new virtual register and live interval.
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unsigned SplitEditor::openIntv() {
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// Create the complement as index 0.
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if (Edit->empty())
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Edit->createEmptyInterval();
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// Create the open interval.
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OpenIdx = Edit->size();
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Edit->createEmptyInterval();
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return OpenIdx;
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}
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void SplitEditor::selectIntv(unsigned Idx) {
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assert(Idx != 0 && "Cannot select the complement interval");
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assert(Idx < Edit->size() && "Can only select previously opened interval");
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DEBUG(dbgs() << " selectIntv " << OpenIdx << " -> " << Idx << '\n');
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OpenIdx = Idx;
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}
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SlotIndex SplitEditor::enterIntvBefore(SlotIndex Idx) {
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assert(OpenIdx && "openIntv not called before enterIntvBefore");
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DEBUG(dbgs() << " enterIntvBefore " << Idx);
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Idx = Idx.getBaseIndex();
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VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx);
|
|
if (!ParentVNI) {
|
|
DEBUG(dbgs() << ": not live\n");
|
|
return Idx;
|
|
}
|
|
DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
|
|
MachineInstr *MI = LIS.getInstructionFromIndex(Idx);
|
|
assert(MI && "enterIntvBefore called with invalid index");
|
|
|
|
VNInfo *VNI = defFromParent(OpenIdx, ParentVNI, Idx, *MI->getParent(), MI);
|
|
return VNI->def;
|
|
}
|
|
|
|
SlotIndex SplitEditor::enterIntvAfter(SlotIndex Idx) {
|
|
assert(OpenIdx && "openIntv not called before enterIntvAfter");
|
|
DEBUG(dbgs() << " enterIntvAfter " << Idx);
|
|
Idx = Idx.getBoundaryIndex();
|
|
VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx);
|
|
if (!ParentVNI) {
|
|
DEBUG(dbgs() << ": not live\n");
|
|
return Idx;
|
|
}
|
|
DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
|
|
MachineInstr *MI = LIS.getInstructionFromIndex(Idx);
|
|
assert(MI && "enterIntvAfter called with invalid index");
|
|
|
|
VNInfo *VNI = defFromParent(OpenIdx, ParentVNI, Idx, *MI->getParent(),
|
|
llvm::next(MachineBasicBlock::iterator(MI)));
|
|
return VNI->def;
|
|
}
|
|
|
|
SlotIndex SplitEditor::enterIntvAtEnd(MachineBasicBlock &MBB) {
|
|
assert(OpenIdx && "openIntv not called before enterIntvAtEnd");
|
|
SlotIndex End = LIS.getMBBEndIdx(&MBB);
|
|
SlotIndex Last = End.getPrevSlot();
|
|
DEBUG(dbgs() << " enterIntvAtEnd BB#" << MBB.getNumber() << ", " << Last);
|
|
VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Last);
|
|
if (!ParentVNI) {
|
|
DEBUG(dbgs() << ": not live\n");
|
|
return End;
|
|
}
|
|
DEBUG(dbgs() << ": valno " << ParentVNI->id);
|
|
VNInfo *VNI = defFromParent(OpenIdx, ParentVNI, Last, MBB,
|
|
SA.getLastSplitPointIter(&MBB));
|
|
RegAssign.insert(VNI->def, End, OpenIdx);
|
|
DEBUG(dump());
|
|
return VNI->def;
|
|
}
|
|
|
|
/// useIntv - indicate that all instructions in MBB should use OpenLI.
|
|
void SplitEditor::useIntv(const MachineBasicBlock &MBB) {
|
|
useIntv(LIS.getMBBStartIdx(&MBB), LIS.getMBBEndIdx(&MBB));
|
|
}
|
|
|
|
void SplitEditor::useIntv(SlotIndex Start, SlotIndex End) {
|
|
assert(OpenIdx && "openIntv not called before useIntv");
|
|
DEBUG(dbgs() << " useIntv [" << Start << ';' << End << "):");
|
|
RegAssign.insert(Start, End, OpenIdx);
|
|
DEBUG(dump());
|
|
}
|
|
|
|
SlotIndex SplitEditor::leaveIntvAfter(SlotIndex Idx) {
|
|
assert(OpenIdx && "openIntv not called before leaveIntvAfter");
|
|
DEBUG(dbgs() << " leaveIntvAfter " << Idx);
|
|
|
|
// The interval must be live beyond the instruction at Idx.
|
|
SlotIndex Boundary = Idx.getBoundaryIndex();
|
|
VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Boundary);
|
|
if (!ParentVNI) {
|
|
DEBUG(dbgs() << ": not live\n");
|
|
return Boundary.getNextSlot();
|
|
}
|
|
DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
|
|
MachineInstr *MI = LIS.getInstructionFromIndex(Boundary);
|
|
assert(MI && "No instruction at index");
|
|
|
|
// In spill mode, make live ranges as short as possible by inserting the copy
|
|
// before MI. This is only possible if that instruction doesn't redefine the
|
|
// value. The inserted COPY is not a kill, and we don't need to recompute
|
|
// the source live range. The spiller also won't try to hoist this copy.
|
|
if (SpillMode && !SlotIndex::isSameInstr(ParentVNI->def, Idx) &&
|
|
MI->readsVirtualRegister(Edit->getReg())) {
|
|
forceRecompute(0, ParentVNI);
|
|
defFromParent(0, ParentVNI, Idx, *MI->getParent(), MI);
|
|
return Idx;
|
|
}
|
|
|
|
VNInfo *VNI = defFromParent(0, ParentVNI, Boundary, *MI->getParent(),
|
|
llvm::next(MachineBasicBlock::iterator(MI)));
|
|
return VNI->def;
|
|
}
|
|
|
|
SlotIndex SplitEditor::leaveIntvBefore(SlotIndex Idx) {
|
|
assert(OpenIdx && "openIntv not called before leaveIntvBefore");
|
|
DEBUG(dbgs() << " leaveIntvBefore " << Idx);
|
|
|
|
// The interval must be live into the instruction at Idx.
|
|
Idx = Idx.getBaseIndex();
|
|
VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx);
|
|
if (!ParentVNI) {
|
|
DEBUG(dbgs() << ": not live\n");
|
|
return Idx.getNextSlot();
|
|
}
|
|
DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
|
|
|
|
MachineInstr *MI = LIS.getInstructionFromIndex(Idx);
|
|
assert(MI && "No instruction at index");
|
|
VNInfo *VNI = defFromParent(0, ParentVNI, Idx, *MI->getParent(), MI);
|
|
return VNI->def;
|
|
}
|
|
|
|
SlotIndex SplitEditor::leaveIntvAtTop(MachineBasicBlock &MBB) {
|
|
assert(OpenIdx && "openIntv not called before leaveIntvAtTop");
|
|
SlotIndex Start = LIS.getMBBStartIdx(&MBB);
|
|
DEBUG(dbgs() << " leaveIntvAtTop BB#" << MBB.getNumber() << ", " << Start);
|
|
|
|
VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Start);
|
|
if (!ParentVNI) {
|
|
DEBUG(dbgs() << ": not live\n");
|
|
return Start;
|
|
}
|
|
|
|
VNInfo *VNI = defFromParent(0, ParentVNI, Start, MBB,
|
|
MBB.SkipPHIsAndLabels(MBB.begin()));
|
|
RegAssign.insert(Start, VNI->def, OpenIdx);
|
|
DEBUG(dump());
|
|
return VNI->def;
|
|
}
|
|
|
|
void SplitEditor::overlapIntv(SlotIndex Start, SlotIndex End) {
|
|
assert(OpenIdx && "openIntv not called before overlapIntv");
|
|
const VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Start);
|
|
assert(ParentVNI == Edit->getParent().getVNInfoBefore(End) &&
|
|
"Parent changes value in extended range");
|
|
assert(LIS.getMBBFromIndex(Start) == LIS.getMBBFromIndex(End) &&
|
|
"Range cannot span basic blocks");
|
|
|
|
// The complement interval will be extended as needed by LRCalc.extend().
|
|
if (ParentVNI)
|
|
forceRecompute(0, ParentVNI);
|
|
DEBUG(dbgs() << " overlapIntv [" << Start << ';' << End << "):");
|
|
RegAssign.insert(Start, End, OpenIdx);
|
|
DEBUG(dump());
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Spill modes
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
void SplitEditor::removeBackCopies(SmallVectorImpl<VNInfo*> &Copies) {
|
|
LiveInterval *LI = &LIS.getInterval(Edit->get(0));
|
|
DEBUG(dbgs() << "Removing " << Copies.size() << " back-copies.\n");
|
|
RegAssignMap::iterator AssignI;
|
|
AssignI.setMap(RegAssign);
|
|
|
|
for (unsigned i = 0, e = Copies.size(); i != e; ++i) {
|
|
VNInfo *VNI = Copies[i];
|
|
SlotIndex Def = VNI->def;
|
|
MachineInstr *MI = LIS.getInstructionFromIndex(Def);
|
|
assert(MI && "No instruction for back-copy");
|
|
|
|
MachineBasicBlock *MBB = MI->getParent();
|
|
MachineBasicBlock::iterator MBBI(MI);
|
|
bool AtBegin;
|
|
do AtBegin = MBBI == MBB->begin();
|
|
while (!AtBegin && (--MBBI)->isDebugValue());
|
|
|
|
DEBUG(dbgs() << "Removing " << Def << '\t' << *MI);
|
|
LI->removeValNo(VNI);
|
|
LIS.RemoveMachineInstrFromMaps(MI);
|
|
MI->eraseFromParent();
|
|
|
|
// Adjust RegAssign if a register assignment is killed at VNI->def. We
|
|
// want to avoid calculating the live range of the source register if
|
|
// possible.
|
|
AssignI.find(Def.getPrevSlot());
|
|
if (!AssignI.valid() || AssignI.start() >= Def)
|
|
continue;
|
|
// If MI doesn't kill the assigned register, just leave it.
|
|
if (AssignI.stop() != Def)
|
|
continue;
|
|
unsigned RegIdx = AssignI.value();
|
|
if (AtBegin || !MBBI->readsVirtualRegister(Edit->getReg())) {
|
|
DEBUG(dbgs() << " cannot find simple kill of RegIdx " << RegIdx << '\n');
|
|
forceRecompute(RegIdx, Edit->getParent().getVNInfoAt(Def));
|
|
} else {
|
|
SlotIndex Kill = LIS.getInstructionIndex(MBBI).getRegSlot();
|
|
DEBUG(dbgs() << " move kill to " << Kill << '\t' << *MBBI);
|
|
AssignI.setStop(Kill);
|
|
}
|
|
}
|
|
}
|
|
|
|
MachineBasicBlock*
|
|
SplitEditor::findShallowDominator(MachineBasicBlock *MBB,
|
|
MachineBasicBlock *DefMBB) {
|
|
if (MBB == DefMBB)
|
|
return MBB;
|
|
assert(MDT.dominates(DefMBB, MBB) && "MBB must be dominated by the def.");
|
|
|
|
const MachineLoopInfo &Loops = SA.Loops;
|
|
const MachineLoop *DefLoop = Loops.getLoopFor(DefMBB);
|
|
MachineDomTreeNode *DefDomNode = MDT[DefMBB];
|
|
|
|
// Best candidate so far.
|
|
MachineBasicBlock *BestMBB = MBB;
|
|
unsigned BestDepth = UINT_MAX;
|
|
|
|
for (;;) {
|
|
const MachineLoop *Loop = Loops.getLoopFor(MBB);
|
|
|
|
// MBB isn't in a loop, it doesn't get any better. All dominators have a
|
|
// higher frequency by definition.
|
|
if (!Loop) {
|
|
DEBUG(dbgs() << "Def in BB#" << DefMBB->getNumber() << " dominates BB#"
|
|
<< MBB->getNumber() << " at depth 0\n");
|
|
return MBB;
|
|
}
|
|
|
|
// We'll never be able to exit the DefLoop.
|
|
if (Loop == DefLoop) {
|
|
DEBUG(dbgs() << "Def in BB#" << DefMBB->getNumber() << " dominates BB#"
|
|
<< MBB->getNumber() << " in the same loop\n");
|
|
return MBB;
|
|
}
|
|
|
|
// Least busy dominator seen so far.
|
|
unsigned Depth = Loop->getLoopDepth();
|
|
if (Depth < BestDepth) {
|
|
BestMBB = MBB;
|
|
BestDepth = Depth;
|
|
DEBUG(dbgs() << "Def in BB#" << DefMBB->getNumber() << " dominates BB#"
|
|
<< MBB->getNumber() << " at depth " << Depth << '\n');
|
|
}
|
|
|
|
// Leave loop by going to the immediate dominator of the loop header.
|
|
// This is a bigger stride than simply walking up the dominator tree.
|
|
MachineDomTreeNode *IDom = MDT[Loop->getHeader()]->getIDom();
|
|
|
|
// Too far up the dominator tree?
|
|
if (!IDom || !MDT.dominates(DefDomNode, IDom))
|
|
return BestMBB;
|
|
|
|
MBB = IDom->getBlock();
|
|
}
|
|
}
|
|
|
|
void SplitEditor::hoistCopiesForSize() {
|
|
// Get the complement interval, always RegIdx 0.
|
|
LiveInterval *LI = &LIS.getInterval(Edit->get(0));
|
|
LiveInterval *Parent = &Edit->getParent();
|
|
|
|
// Track the nearest common dominator for all back-copies for each ParentVNI,
|
|
// indexed by ParentVNI->id.
|
|
typedef std::pair<MachineBasicBlock*, SlotIndex> DomPair;
|
|
SmallVector<DomPair, 8> NearestDom(Parent->getNumValNums());
|
|
|
|
// Find the nearest common dominator for parent values with multiple
|
|
// back-copies. If a single back-copy dominates, put it in DomPair.second.
|
|
for (LiveInterval::vni_iterator VI = LI->vni_begin(), VE = LI->vni_end();
|
|
VI != VE; ++VI) {
|
|
VNInfo *VNI = *VI;
|
|
if (VNI->isUnused())
|
|
continue;
|
|
VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(VNI->def);
|
|
assert(ParentVNI && "Parent not live at complement def");
|
|
|
|
// Don't hoist remats. The complement is probably going to disappear
|
|
// completely anyway.
|
|
if (Edit->didRematerialize(ParentVNI))
|
|
continue;
|
|
|
|
MachineBasicBlock *ValMBB = LIS.getMBBFromIndex(VNI->def);
|
|
DomPair &Dom = NearestDom[ParentVNI->id];
|
|
|
|
// Keep directly defined parent values. This is either a PHI or an
|
|
// instruction in the complement range. All other copies of ParentVNI
|
|
// should be eliminated.
|
|
if (VNI->def == ParentVNI->def) {
|
|
DEBUG(dbgs() << "Direct complement def at " << VNI->def << '\n');
|
|
Dom = DomPair(ValMBB, VNI->def);
|
|
continue;
|
|
}
|
|
// Skip the singly mapped values. There is nothing to gain from hoisting a
|
|
// single back-copy.
|
|
if (Values.lookup(std::make_pair(0, ParentVNI->id)).getPointer()) {
|
|
DEBUG(dbgs() << "Single complement def at " << VNI->def << '\n');
|
|
continue;
|
|
}
|
|
|
|
if (!Dom.first) {
|
|
// First time we see ParentVNI. VNI dominates itself.
|
|
Dom = DomPair(ValMBB, VNI->def);
|
|
} else if (Dom.first == ValMBB) {
|
|
// Two defs in the same block. Pick the earlier def.
|
|
if (!Dom.second.isValid() || VNI->def < Dom.second)
|
|
Dom.second = VNI->def;
|
|
} else {
|
|
// Different basic blocks. Check if one dominates.
|
|
MachineBasicBlock *Near =
|
|
MDT.findNearestCommonDominator(Dom.first, ValMBB);
|
|
if (Near == ValMBB)
|
|
// Def ValMBB dominates.
|
|
Dom = DomPair(ValMBB, VNI->def);
|
|
else if (Near != Dom.first)
|
|
// None dominate. Hoist to common dominator, need new def.
|
|
Dom = DomPair(Near, SlotIndex());
|
|
}
|
|
|
|
DEBUG(dbgs() << "Multi-mapped complement " << VNI->id << '@' << VNI->def
|
|
<< " for parent " << ParentVNI->id << '@' << ParentVNI->def
|
|
<< " hoist to BB#" << Dom.first->getNumber() << ' '
|
|
<< Dom.second << '\n');
|
|
}
|
|
|
|
// Insert the hoisted copies.
|
|
for (unsigned i = 0, e = Parent->getNumValNums(); i != e; ++i) {
|
|
DomPair &Dom = NearestDom[i];
|
|
if (!Dom.first || Dom.second.isValid())
|
|
continue;
|
|
// This value needs a hoisted copy inserted at the end of Dom.first.
|
|
VNInfo *ParentVNI = Parent->getValNumInfo(i);
|
|
MachineBasicBlock *DefMBB = LIS.getMBBFromIndex(ParentVNI->def);
|
|
// Get a less loopy dominator than Dom.first.
|
|
Dom.first = findShallowDominator(Dom.first, DefMBB);
|
|
SlotIndex Last = LIS.getMBBEndIdx(Dom.first).getPrevSlot();
|
|
Dom.second =
|
|
defFromParent(0, ParentVNI, Last, *Dom.first,
|
|
SA.getLastSplitPointIter(Dom.first))->def;
|
|
}
|
|
|
|
// Remove redundant back-copies that are now known to be dominated by another
|
|
// def with the same value.
|
|
SmallVector<VNInfo*, 8> BackCopies;
|
|
for (LiveInterval::vni_iterator VI = LI->vni_begin(), VE = LI->vni_end();
|
|
VI != VE; ++VI) {
|
|
VNInfo *VNI = *VI;
|
|
if (VNI->isUnused())
|
|
continue;
|
|
VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(VNI->def);
|
|
const DomPair &Dom = NearestDom[ParentVNI->id];
|
|
if (!Dom.first || Dom.second == VNI->def)
|
|
continue;
|
|
BackCopies.push_back(VNI);
|
|
forceRecompute(0, ParentVNI);
|
|
}
|
|
removeBackCopies(BackCopies);
|
|
}
|
|
|
|
|
|
/// transferValues - Transfer all possible values to the new live ranges.
|
|
/// Values that were rematerialized are left alone, they need LRCalc.extend().
|
|
bool SplitEditor::transferValues() {
|
|
bool Skipped = false;
|
|
RegAssignMap::const_iterator AssignI = RegAssign.begin();
|
|
for (LiveInterval::const_iterator ParentI = Edit->getParent().begin(),
|
|
ParentE = Edit->getParent().end(); ParentI != ParentE; ++ParentI) {
|
|
DEBUG(dbgs() << " blit " << *ParentI << ':');
|
|
VNInfo *ParentVNI = ParentI->valno;
|
|
// RegAssign has holes where RegIdx 0 should be used.
|
|
SlotIndex Start = ParentI->start;
|
|
AssignI.advanceTo(Start);
|
|
do {
|
|
unsigned RegIdx;
|
|
SlotIndex End = ParentI->end;
|
|
if (!AssignI.valid()) {
|
|
RegIdx = 0;
|
|
} else if (AssignI.start() <= Start) {
|
|
RegIdx = AssignI.value();
|
|
if (AssignI.stop() < End) {
|
|
End = AssignI.stop();
|
|
++AssignI;
|
|
}
|
|
} else {
|
|
RegIdx = 0;
|
|
End = std::min(End, AssignI.start());
|
|
}
|
|
|
|
// The interval [Start;End) is continuously mapped to RegIdx, ParentVNI.
|
|
DEBUG(dbgs() << " [" << Start << ';' << End << ")=" << RegIdx);
|
|
LiveRange &LR = LIS.getInterval(Edit->get(RegIdx));
|
|
|
|
// Check for a simply defined value that can be blitted directly.
|
|
ValueForcePair VFP = Values.lookup(std::make_pair(RegIdx, ParentVNI->id));
|
|
if (VNInfo *VNI = VFP.getPointer()) {
|
|
DEBUG(dbgs() << ':' << VNI->id);
|
|
LR.addSegment(LiveInterval::Segment(Start, End, VNI));
|
|
Start = End;
|
|
continue;
|
|
}
|
|
|
|
// Skip values with forced recomputation.
|
|
if (VFP.getInt()) {
|
|
DEBUG(dbgs() << "(recalc)");
|
|
Skipped = true;
|
|
Start = End;
|
|
continue;
|
|
}
|
|
|
|
LiveRangeCalc &LRC = getLRCalc(RegIdx);
|
|
|
|
// This value has multiple defs in RegIdx, but it wasn't rematerialized,
|
|
// so the live range is accurate. Add live-in blocks in [Start;End) to the
|
|
// LiveInBlocks.
|
|
MachineFunction::iterator MBB = LIS.getMBBFromIndex(Start);
|
|
SlotIndex BlockStart, BlockEnd;
|
|
tie(BlockStart, BlockEnd) = LIS.getSlotIndexes()->getMBBRange(MBB);
|
|
|
|
// The first block may be live-in, or it may have its own def.
|
|
if (Start != BlockStart) {
|
|
VNInfo *VNI = LR.extendInBlock(BlockStart, std::min(BlockEnd, End));
|
|
assert(VNI && "Missing def for complex mapped value");
|
|
DEBUG(dbgs() << ':' << VNI->id << "*BB#" << MBB->getNumber());
|
|
// MBB has its own def. Is it also live-out?
|
|
if (BlockEnd <= End)
|
|
LRC.setLiveOutValue(MBB, VNI);
|
|
|
|
// Skip to the next block for live-in.
|
|
++MBB;
|
|
BlockStart = BlockEnd;
|
|
}
|
|
|
|
// Handle the live-in blocks covered by [Start;End).
|
|
assert(Start <= BlockStart && "Expected live-in block");
|
|
while (BlockStart < End) {
|
|
DEBUG(dbgs() << ">BB#" << MBB->getNumber());
|
|
BlockEnd = LIS.getMBBEndIdx(MBB);
|
|
if (BlockStart == ParentVNI->def) {
|
|
// This block has the def of a parent PHI, so it isn't live-in.
|
|
assert(ParentVNI->isPHIDef() && "Non-phi defined at block start?");
|
|
VNInfo *VNI = LR.extendInBlock(BlockStart, std::min(BlockEnd, End));
|
|
assert(VNI && "Missing def for complex mapped parent PHI");
|
|
if (End >= BlockEnd)
|
|
LRC.setLiveOutValue(MBB, VNI); // Live-out as well.
|
|
} else {
|
|
// This block needs a live-in value. The last block covered may not
|
|
// be live-out.
|
|
if (End < BlockEnd)
|
|
LRC.addLiveInBlock(LR, MDT[MBB], End);
|
|
else {
|
|
// Live-through, and we don't know the value.
|
|
LRC.addLiveInBlock(LR, MDT[MBB]);
|
|
LRC.setLiveOutValue(MBB, 0);
|
|
}
|
|
}
|
|
BlockStart = BlockEnd;
|
|
++MBB;
|
|
}
|
|
Start = End;
|
|
} while (Start != ParentI->end);
|
|
DEBUG(dbgs() << '\n');
|
|
}
|
|
|
|
LRCalc[0].calculateValues();
|
|
if (SpillMode)
|
|
LRCalc[1].calculateValues();
|
|
|
|
return Skipped;
|
|
}
|
|
|
|
void SplitEditor::extendPHIKillRanges() {
|
|
// Extend live ranges to be live-out for successor PHI values.
|
|
for (LiveInterval::const_vni_iterator I = Edit->getParent().vni_begin(),
|
|
E = Edit->getParent().vni_end(); I != E; ++I) {
|
|
const VNInfo *PHIVNI = *I;
|
|
if (PHIVNI->isUnused() || !PHIVNI->isPHIDef())
|
|
continue;
|
|
unsigned RegIdx = RegAssign.lookup(PHIVNI->def);
|
|
LiveRange &LR = LIS.getInterval(Edit->get(RegIdx));
|
|
LiveRangeCalc &LRC = getLRCalc(RegIdx);
|
|
MachineBasicBlock *MBB = LIS.getMBBFromIndex(PHIVNI->def);
|
|
for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(),
|
|
PE = MBB->pred_end(); PI != PE; ++PI) {
|
|
SlotIndex End = LIS.getMBBEndIdx(*PI);
|
|
SlotIndex LastUse = End.getPrevSlot();
|
|
// The predecessor may not have a live-out value. That is OK, like an
|
|
// undef PHI operand.
|
|
if (Edit->getParent().liveAt(LastUse)) {
|
|
assert(RegAssign.lookup(LastUse) == RegIdx &&
|
|
"Different register assignment in phi predecessor");
|
|
LRC.extend(LR, End);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
/// rewriteAssigned - Rewrite all uses of Edit->getReg().
|
|
void SplitEditor::rewriteAssigned(bool ExtendRanges) {
|
|
for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(Edit->getReg()),
|
|
RE = MRI.reg_end(); RI != RE;) {
|
|
MachineOperand &MO = RI.getOperand();
|
|
MachineInstr *MI = MO.getParent();
|
|
++RI;
|
|
// LiveDebugVariables should have handled all DBG_VALUE instructions.
|
|
if (MI->isDebugValue()) {
|
|
DEBUG(dbgs() << "Zapping " << *MI);
|
|
MO.setReg(0);
|
|
continue;
|
|
}
|
|
|
|
// <undef> operands don't really read the register, so it doesn't matter
|
|
// which register we choose. When the use operand is tied to a def, we must
|
|
// use the same register as the def, so just do that always.
|
|
SlotIndex Idx = LIS.getInstructionIndex(MI);
|
|
if (MO.isDef() || MO.isUndef())
|
|
Idx = Idx.getRegSlot(MO.isEarlyClobber());
|
|
|
|
// Rewrite to the mapped register at Idx.
|
|
unsigned RegIdx = RegAssign.lookup(Idx);
|
|
LiveInterval *LI = &LIS.getInterval(Edit->get(RegIdx));
|
|
MO.setReg(LI->reg);
|
|
DEBUG(dbgs() << " rewr BB#" << MI->getParent()->getNumber() << '\t'
|
|
<< Idx << ':' << RegIdx << '\t' << *MI);
|
|
|
|
// Extend liveness to Idx if the instruction reads reg.
|
|
if (!ExtendRanges || MO.isUndef())
|
|
continue;
|
|
|
|
// Skip instructions that don't read Reg.
|
|
if (MO.isDef()) {
|
|
if (!MO.getSubReg() && !MO.isEarlyClobber())
|
|
continue;
|
|
// We may wan't to extend a live range for a partial redef, or for a use
|
|
// tied to an early clobber.
|
|
Idx = Idx.getPrevSlot();
|
|
if (!Edit->getParent().liveAt(Idx))
|
|
continue;
|
|
} else
|
|
Idx = Idx.getRegSlot(true);
|
|
|
|
getLRCalc(RegIdx).extend(*LI, Idx.getNextSlot());
|
|
}
|
|
}
|
|
|
|
void SplitEditor::deleteRematVictims() {
|
|
SmallVector<MachineInstr*, 8> Dead;
|
|
for (LiveRangeEdit::iterator I = Edit->begin(), E = Edit->end(); I != E; ++I){
|
|
LiveInterval *LI = &LIS.getInterval(*I);
|
|
for (LiveInterval::const_iterator LII = LI->begin(), LIE = LI->end();
|
|
LII != LIE; ++LII) {
|
|
// Dead defs end at the dead slot.
|
|
if (LII->end != LII->valno->def.getDeadSlot())
|
|
continue;
|
|
MachineInstr *MI = LIS.getInstructionFromIndex(LII->valno->def);
|
|
assert(MI && "Missing instruction for dead def");
|
|
MI->addRegisterDead(LI->reg, &TRI);
|
|
|
|
if (!MI->allDefsAreDead())
|
|
continue;
|
|
|
|
DEBUG(dbgs() << "All defs dead: " << *MI);
|
|
Dead.push_back(MI);
|
|
}
|
|
}
|
|
|
|
if (Dead.empty())
|
|
return;
|
|
|
|
Edit->eliminateDeadDefs(Dead);
|
|
}
|
|
|
|
void SplitEditor::finish(SmallVectorImpl<unsigned> *LRMap) {
|
|
++NumFinished;
|
|
|
|
// At this point, the live intervals in Edit contain VNInfos corresponding to
|
|
// the inserted copies.
|
|
|
|
// Add the original defs from the parent interval.
|
|
for (LiveInterval::const_vni_iterator I = Edit->getParent().vni_begin(),
|
|
E = Edit->getParent().vni_end(); I != E; ++I) {
|
|
const VNInfo *ParentVNI = *I;
|
|
if (ParentVNI->isUnused())
|
|
continue;
|
|
unsigned RegIdx = RegAssign.lookup(ParentVNI->def);
|
|
defValue(RegIdx, ParentVNI, ParentVNI->def);
|
|
|
|
// Force rematted values to be recomputed everywhere.
|
|
// The new live ranges may be truncated.
|
|
if (Edit->didRematerialize(ParentVNI))
|
|
for (unsigned i = 0, e = Edit->size(); i != e; ++i)
|
|
forceRecompute(i, ParentVNI);
|
|
}
|
|
|
|
// Hoist back-copies to the complement interval when in spill mode.
|
|
switch (SpillMode) {
|
|
case SM_Partition:
|
|
// Leave all back-copies as is.
|
|
break;
|
|
case SM_Size:
|
|
hoistCopiesForSize();
|
|
break;
|
|
case SM_Speed:
|
|
llvm_unreachable("Spill mode 'speed' not implemented yet");
|
|
}
|
|
|
|
// Transfer the simply mapped values, check if any are skipped.
|
|
bool Skipped = transferValues();
|
|
if (Skipped)
|
|
extendPHIKillRanges();
|
|
else
|
|
++NumSimple;
|
|
|
|
// Rewrite virtual registers, possibly extending ranges.
|
|
rewriteAssigned(Skipped);
|
|
|
|
// Delete defs that were rematted everywhere.
|
|
if (Skipped)
|
|
deleteRematVictims();
|
|
|
|
// Get rid of unused values and set phi-kill flags.
|
|
for (LiveRangeEdit::iterator I = Edit->begin(), E = Edit->end(); I != E; ++I) {
|
|
LiveInterval &LI = LIS.getInterval(*I);
|
|
LI.RenumberValues();
|
|
}
|
|
|
|
// Provide a reverse mapping from original indices to Edit ranges.
|
|
if (LRMap) {
|
|
LRMap->clear();
|
|
for (unsigned i = 0, e = Edit->size(); i != e; ++i)
|
|
LRMap->push_back(i);
|
|
}
|
|
|
|
// Now check if any registers were separated into multiple components.
|
|
ConnectedVNInfoEqClasses ConEQ(LIS);
|
|
for (unsigned i = 0, e = Edit->size(); i != e; ++i) {
|
|
// Don't use iterators, they are invalidated by create() below.
|
|
LiveInterval *li = &LIS.getInterval(Edit->get(i));
|
|
unsigned NumComp = ConEQ.Classify(li);
|
|
if (NumComp <= 1)
|
|
continue;
|
|
DEBUG(dbgs() << " " << NumComp << " components: " << *li << '\n');
|
|
SmallVector<LiveInterval*, 8> dups;
|
|
dups.push_back(li);
|
|
for (unsigned j = 1; j != NumComp; ++j)
|
|
dups.push_back(&Edit->createEmptyInterval());
|
|
ConEQ.Distribute(&dups[0], MRI);
|
|
// The new intervals all map back to i.
|
|
if (LRMap)
|
|
LRMap->resize(Edit->size(), i);
|
|
}
|
|
|
|
// Calculate spill weight and allocation hints for new intervals.
|
|
Edit->calculateRegClassAndHint(VRM.getMachineFunction(), SA.Loops, MBFI);
|
|
|
|
assert(!LRMap || LRMap->size() == Edit->size());
|
|
}
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Single Block Splitting
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
bool SplitAnalysis::shouldSplitSingleBlock(const BlockInfo &BI,
|
|
bool SingleInstrs) const {
|
|
// Always split for multiple instructions.
|
|
if (!BI.isOneInstr())
|
|
return true;
|
|
// Don't split for single instructions unless explicitly requested.
|
|
if (!SingleInstrs)
|
|
return false;
|
|
// Splitting a live-through range always makes progress.
|
|
if (BI.LiveIn && BI.LiveOut)
|
|
return true;
|
|
// No point in isolating a copy. It has no register class constraints.
|
|
if (LIS.getInstructionFromIndex(BI.FirstInstr)->isCopyLike())
|
|
return false;
|
|
// Finally, don't isolate an end point that was created by earlier splits.
|
|
return isOriginalEndpoint(BI.FirstInstr);
|
|
}
|
|
|
|
void SplitEditor::splitSingleBlock(const SplitAnalysis::BlockInfo &BI) {
|
|
openIntv();
|
|
SlotIndex LastSplitPoint = SA.getLastSplitPoint(BI.MBB->getNumber());
|
|
SlotIndex SegStart = enterIntvBefore(std::min(BI.FirstInstr,
|
|
LastSplitPoint));
|
|
if (!BI.LiveOut || BI.LastInstr < LastSplitPoint) {
|
|
useIntv(SegStart, leaveIntvAfter(BI.LastInstr));
|
|
} else {
|
|
// The last use is after the last valid split point.
|
|
SlotIndex SegStop = leaveIntvBefore(LastSplitPoint);
|
|
useIntv(SegStart, SegStop);
|
|
overlapIntv(SegStop, BI.LastInstr);
|
|
}
|
|
}
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Global Live Range Splitting Support
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// These methods support a method of global live range splitting that uses a
|
|
// global algorithm to decide intervals for CFG edges. They will insert split
|
|
// points and color intervals in basic blocks while avoiding interference.
|
|
//
|
|
// Note that splitSingleBlock is also useful for blocks where both CFG edges
|
|
// are on the stack.
|
|
|
|
void SplitEditor::splitLiveThroughBlock(unsigned MBBNum,
|
|
unsigned IntvIn, SlotIndex LeaveBefore,
|
|
unsigned IntvOut, SlotIndex EnterAfter){
|
|
SlotIndex Start, Stop;
|
|
tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(MBBNum);
|
|
|
|
DEBUG(dbgs() << "BB#" << MBBNum << " [" << Start << ';' << Stop
|
|
<< ") intf " << LeaveBefore << '-' << EnterAfter
|
|
<< ", live-through " << IntvIn << " -> " << IntvOut);
|
|
|
|
assert((IntvIn || IntvOut) && "Use splitSingleBlock for isolated blocks");
|
|
|
|
assert((!LeaveBefore || LeaveBefore < Stop) && "Interference after block");
|
|
assert((!IntvIn || !LeaveBefore || LeaveBefore > Start) && "Impossible intf");
|
|
assert((!EnterAfter || EnterAfter >= Start) && "Interference before block");
|
|
|
|
MachineBasicBlock *MBB = VRM.getMachineFunction().getBlockNumbered(MBBNum);
|
|
|
|
if (!IntvOut) {
|
|
DEBUG(dbgs() << ", spill on entry.\n");
|
|
//
|
|
// <<<<<<<<< Possible LeaveBefore interference.
|
|
// |-----------| Live through.
|
|
// -____________ Spill on entry.
|
|
//
|
|
selectIntv(IntvIn);
|
|
SlotIndex Idx = leaveIntvAtTop(*MBB);
|
|
assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
|
|
(void)Idx;
|
|
return;
|
|
}
|
|
|
|
if (!IntvIn) {
|
|
DEBUG(dbgs() << ", reload on exit.\n");
|
|
//
|
|
// >>>>>>> Possible EnterAfter interference.
|
|
// |-----------| Live through.
|
|
// ___________-- Reload on exit.
|
|
//
|
|
selectIntv(IntvOut);
|
|
SlotIndex Idx = enterIntvAtEnd(*MBB);
|
|
assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
|
|
(void)Idx;
|
|
return;
|
|
}
|
|
|
|
if (IntvIn == IntvOut && !LeaveBefore && !EnterAfter) {
|
|
DEBUG(dbgs() << ", straight through.\n");
|
|
//
|
|
// |-----------| Live through.
|
|
// ------------- Straight through, same intv, no interference.
|
|
//
|
|
selectIntv(IntvOut);
|
|
useIntv(Start, Stop);
|
|
return;
|
|
}
|
|
|
|
// We cannot legally insert splits after LSP.
|
|
SlotIndex LSP = SA.getLastSplitPoint(MBBNum);
|
|
assert((!IntvOut || !EnterAfter || EnterAfter < LSP) && "Impossible intf");
|
|
|
|
if (IntvIn != IntvOut && (!LeaveBefore || !EnterAfter ||
|
|
LeaveBefore.getBaseIndex() > EnterAfter.getBoundaryIndex())) {
|
|
DEBUG(dbgs() << ", switch avoiding interference.\n");
|
|
//
|
|
// >>>> <<<< Non-overlapping EnterAfter/LeaveBefore interference.
|
|
// |-----------| Live through.
|
|
// ------======= Switch intervals between interference.
|
|
//
|
|
selectIntv(IntvOut);
|
|
SlotIndex Idx;
|
|
if (LeaveBefore && LeaveBefore < LSP) {
|
|
Idx = enterIntvBefore(LeaveBefore);
|
|
useIntv(Idx, Stop);
|
|
} else {
|
|
Idx = enterIntvAtEnd(*MBB);
|
|
}
|
|
selectIntv(IntvIn);
|
|
useIntv(Start, Idx);
|
|
assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
|
|
assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
|
|
return;
|
|
}
|
|
|
|
DEBUG(dbgs() << ", create local intv for interference.\n");
|
|
//
|
|
// >>><><><><<<< Overlapping EnterAfter/LeaveBefore interference.
|
|
// |-----------| Live through.
|
|
// ==---------== Switch intervals before/after interference.
|
|
//
|
|
assert(LeaveBefore <= EnterAfter && "Missed case");
|
|
|
|
selectIntv(IntvOut);
|
|
SlotIndex Idx = enterIntvAfter(EnterAfter);
|
|
useIntv(Idx, Stop);
|
|
assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
|
|
|
|
selectIntv(IntvIn);
|
|
Idx = leaveIntvBefore(LeaveBefore);
|
|
useIntv(Start, Idx);
|
|
assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
|
|
}
|
|
|
|
|
|
void SplitEditor::splitRegInBlock(const SplitAnalysis::BlockInfo &BI,
|
|
unsigned IntvIn, SlotIndex LeaveBefore) {
|
|
SlotIndex Start, Stop;
|
|
tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(BI.MBB);
|
|
|
|
DEBUG(dbgs() << "BB#" << BI.MBB->getNumber() << " [" << Start << ';' << Stop
|
|
<< "), uses " << BI.FirstInstr << '-' << BI.LastInstr
|
|
<< ", reg-in " << IntvIn << ", leave before " << LeaveBefore
|
|
<< (BI.LiveOut ? ", stack-out" : ", killed in block"));
|
|
|
|
assert(IntvIn && "Must have register in");
|
|
assert(BI.LiveIn && "Must be live-in");
|
|
assert((!LeaveBefore || LeaveBefore > Start) && "Bad interference");
|
|
|
|
if (!BI.LiveOut && (!LeaveBefore || LeaveBefore >= BI.LastInstr)) {
|
|
DEBUG(dbgs() << " before interference.\n");
|
|
//
|
|
// <<< Interference after kill.
|
|
// |---o---x | Killed in block.
|
|
// ========= Use IntvIn everywhere.
|
|
//
|
|
selectIntv(IntvIn);
|
|
useIntv(Start, BI.LastInstr);
|
|
return;
|
|
}
|
|
|
|
SlotIndex LSP = SA.getLastSplitPoint(BI.MBB->getNumber());
|
|
|
|
if (!LeaveBefore || LeaveBefore > BI.LastInstr.getBoundaryIndex()) {
|
|
//
|
|
// <<< Possible interference after last use.
|
|
// |---o---o---| Live-out on stack.
|
|
// =========____ Leave IntvIn after last use.
|
|
//
|
|
// < Interference after last use.
|
|
// |---o---o--o| Live-out on stack, late last use.
|
|
// ============ Copy to stack after LSP, overlap IntvIn.
|
|
// \_____ Stack interval is live-out.
|
|
//
|
|
if (BI.LastInstr < LSP) {
|
|
DEBUG(dbgs() << ", spill after last use before interference.\n");
|
|
selectIntv(IntvIn);
|
|
SlotIndex Idx = leaveIntvAfter(BI.LastInstr);
|
|
useIntv(Start, Idx);
|
|
assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
|
|
} else {
|
|
DEBUG(dbgs() << ", spill before last split point.\n");
|
|
selectIntv(IntvIn);
|
|
SlotIndex Idx = leaveIntvBefore(LSP);
|
|
overlapIntv(Idx, BI.LastInstr);
|
|
useIntv(Start, Idx);
|
|
assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
|
|
}
|
|
return;
|
|
}
|
|
|
|
// The interference is overlapping somewhere we wanted to use IntvIn. That
|
|
// means we need to create a local interval that can be allocated a
|
|
// different register.
|
|
unsigned LocalIntv = openIntv();
|
|
(void)LocalIntv;
|
|
DEBUG(dbgs() << ", creating local interval " << LocalIntv << ".\n");
|
|
|
|
if (!BI.LiveOut || BI.LastInstr < LSP) {
|
|
//
|
|
// <<<<<<< Interference overlapping uses.
|
|
// |---o---o---| Live-out on stack.
|
|
// =====----____ Leave IntvIn before interference, then spill.
|
|
//
|
|
SlotIndex To = leaveIntvAfter(BI.LastInstr);
|
|
SlotIndex From = enterIntvBefore(LeaveBefore);
|
|
useIntv(From, To);
|
|
selectIntv(IntvIn);
|
|
useIntv(Start, From);
|
|
assert((!LeaveBefore || From <= LeaveBefore) && "Interference");
|
|
return;
|
|
}
|
|
|
|
// <<<<<<< Interference overlapping uses.
|
|
// |---o---o--o| Live-out on stack, late last use.
|
|
// =====------- Copy to stack before LSP, overlap LocalIntv.
|
|
// \_____ Stack interval is live-out.
|
|
//
|
|
SlotIndex To = leaveIntvBefore(LSP);
|
|
overlapIntv(To, BI.LastInstr);
|
|
SlotIndex From = enterIntvBefore(std::min(To, LeaveBefore));
|
|
useIntv(From, To);
|
|
selectIntv(IntvIn);
|
|
useIntv(Start, From);
|
|
assert((!LeaveBefore || From <= LeaveBefore) && "Interference");
|
|
}
|
|
|
|
void SplitEditor::splitRegOutBlock(const SplitAnalysis::BlockInfo &BI,
|
|
unsigned IntvOut, SlotIndex EnterAfter) {
|
|
SlotIndex Start, Stop;
|
|
tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(BI.MBB);
|
|
|
|
DEBUG(dbgs() << "BB#" << BI.MBB->getNumber() << " [" << Start << ';' << Stop
|
|
<< "), uses " << BI.FirstInstr << '-' << BI.LastInstr
|
|
<< ", reg-out " << IntvOut << ", enter after " << EnterAfter
|
|
<< (BI.LiveIn ? ", stack-in" : ", defined in block"));
|
|
|
|
SlotIndex LSP = SA.getLastSplitPoint(BI.MBB->getNumber());
|
|
|
|
assert(IntvOut && "Must have register out");
|
|
assert(BI.LiveOut && "Must be live-out");
|
|
assert((!EnterAfter || EnterAfter < LSP) && "Bad interference");
|
|
|
|
if (!BI.LiveIn && (!EnterAfter || EnterAfter <= BI.FirstInstr)) {
|
|
DEBUG(dbgs() << " after interference.\n");
|
|
//
|
|
// >>>> Interference before def.
|
|
// | o---o---| Defined in block.
|
|
// ========= Use IntvOut everywhere.
|
|
//
|
|
selectIntv(IntvOut);
|
|
useIntv(BI.FirstInstr, Stop);
|
|
return;
|
|
}
|
|
|
|
if (!EnterAfter || EnterAfter < BI.FirstInstr.getBaseIndex()) {
|
|
DEBUG(dbgs() << ", reload after interference.\n");
|
|
//
|
|
// >>>> Interference before def.
|
|
// |---o---o---| Live-through, stack-in.
|
|
// ____========= Enter IntvOut before first use.
|
|
//
|
|
selectIntv(IntvOut);
|
|
SlotIndex Idx = enterIntvBefore(std::min(LSP, BI.FirstInstr));
|
|
useIntv(Idx, Stop);
|
|
assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
|
|
return;
|
|
}
|
|
|
|
// The interference is overlapping somewhere we wanted to use IntvOut. That
|
|
// means we need to create a local interval that can be allocated a
|
|
// different register.
|
|
DEBUG(dbgs() << ", interference overlaps uses.\n");
|
|
//
|
|
// >>>>>>> Interference overlapping uses.
|
|
// |---o---o---| Live-through, stack-in.
|
|
// ____---====== Create local interval for interference range.
|
|
//
|
|
selectIntv(IntvOut);
|
|
SlotIndex Idx = enterIntvAfter(EnterAfter);
|
|
useIntv(Idx, Stop);
|
|
assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
|
|
|
|
openIntv();
|
|
SlotIndex From = enterIntvBefore(std::min(Idx, BI.FirstInstr));
|
|
useIntv(From, Idx);
|
|
}
|