mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-25 20:23:11 +01:00
ced90969e3
Previously, the parsing of the 'subu $reg, ($reg,) imm' relied on a parser which also rendered the operand to the instruction. In some cases the general parser could construct an MCExpr which was not a MCConstantExpr which MipsAsmParser was expecting. Address this by altering the special handling to cope with unexpected inputs and fine-tune the handling of cases where an register name that is not available in the current ABI is regarded as not a match for the custom parser but also not as an outright error. Also enforces the binutils restriction that only constants are accepted. This partially resolves PR34391. Thanks to Ed Maste for reporting the issue! Reviewers: nitesh.jain, arichardson Differential Revision: https://reviews.llvm.org/D37476 llvm-svn: 315310
36 lines
1.3 KiB
ArmAsm
36 lines
1.3 KiB
ArmAsm
# RUN: llvm-mc -arch=mips -mcpu=mips32r2 %s -show-inst | FileCheck %s
|
|
|
|
# Test that subu accepts constant operands and inverts them when
|
|
# rendering the operand.
|
|
|
|
subu $4, $4, 4 # CHECK: ADDiu
|
|
# CHECK; Imm:-4
|
|
subu $gp, $gp, 4 # CHECK: ADDiu
|
|
# CHECK; Imm:-4
|
|
subu $sp, $sp, 4 # CHECK: ADDiu
|
|
# CHECK; Imm:-4
|
|
subu $4, $4, -4 # CHECK: ADDiu
|
|
# CHECK; Imm:4
|
|
subu $gp, $gp, -4 # CHECK: ADDiu
|
|
# CHECK; Imm:4
|
|
subu $sp, $sp, -4 # CHECK: ADDiu
|
|
# CHECK; Imm:4
|
|
subu $sp, $sp, -(4 + 4) # CHECK: ADDiu
|
|
# CHECK: Imm:8
|
|
|
|
subu $4, 8 # CHECK: ADDiu
|
|
# CHECK; Imm:-8
|
|
subu $gp, 8 # CHECK: ADDiu
|
|
# CHECK; Imm:-8
|
|
subu $sp, 8 # CHECK: ADDiu
|
|
# CHECK; Imm:-8
|
|
subu $4, -8 # CHECK: ADDiu
|
|
# CHECK; Imm:8
|
|
subu $gp, -8 # CHECK: ADDiu
|
|
# CHECK; Imm:8
|
|
subu $sp, -8 # CHECK: ADDiu
|
|
# CHECK; Imm:8
|
|
subu $sp, -(4 + 4) # CHECK: ADDiu
|
|
# CHECK: Imm:8
|
|
|