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03acdd5b32
The IBM BG/Q supercomputer's A2 cores have a hardware prefetching unit, the L1P, but it does not prefetch directly into the A2's L1 cache. Instead, it prefetches into its own L1P buffer, and the latency to access that buffer is significantly higher than that to the L1 cache (although smaller than the latency to the L2 cache). As a result, especially when multiple hardware threads are not actively busy, explicitly prefetching data into the L1 cache is advantageous. I've been using this pass out-of-tree for data prefetching on the BG/Q for well over a year, and it has worked quite well. It is enabled by default only for the BG/Q, but can be enabled for other cores as well via a command-line option. Eventually, we might want to add some TTI interfaces and move this into Transforms/Scalar (there is nothing particularly target dependent about it, although only machines like the BG/Q will benefit from its simplistic strategy). llvm-svn: 229966
30 lines
960 B
LLVM
30 lines
960 B
LLVM
; RUN: llc -mcpu=a2 < %s | FileCheck %s
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target datalayout = "E-m:e-i64:64-n32:64"
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target triple = "powerpc64-bgq-linux"
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; Function Attrs: nounwind
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define void @foo(double* nocapture %a, double* nocapture readonly %b) #0 {
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entry:
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br label %for.body
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for.body: ; preds = %for.body, %entry
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%indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
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%arrayidx = getelementptr inbounds double* %b, i64 %indvars.iv
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%0 = load double* %arrayidx, align 8
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%add = fadd double %0, 1.000000e+00
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%arrayidx2 = getelementptr inbounds double* %a, i64 %indvars.iv
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store double %add, double* %arrayidx2, align 8
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%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
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%exitcond = icmp eq i64 %indvars.iv.next, 1600
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br i1 %exitcond, label %for.end, label %for.body
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for.end: ; preds = %for.body
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ret void
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; CHECK-LABEL: @foo
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; CHECK: dcbt
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}
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attributes #0 = { nounwind }
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