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930e5f41df
int->fp conversions on PPC must be done through memory loads and stores. On a modern core, this process begins by storing the int value to memory, then loading it using a (sometimes special) FP load instruction. Unfortunately, we would do this even when the value to be converted was itself a load, and we can just use that same memory location instead of copying it to another first. There is a slight complication when handling int_to_fp(fp_to_int(x)) pairs, because the fp_to_int operand has not been lowered when the int_to_fp is being lowered. We handle this specially by invoking fp_to_int's lowering logic (partially) and getting the necessary memory location (some trivial refactoring was done to make this possible). This is all somewhat ugly, and it would be nice if some later CodeGen stage could just clean this stuff up, but because doing so would involve modifying target-specific nodes (or instructions), it is not immediately clear how that would work. Also, remove a related entry from the README.txt for which we now generate reasonable code. llvm-svn: 225301
97 lines
2.3 KiB
LLVM
97 lines
2.3 KiB
LLVM
; RUN: llc -mcpu=a2 < %s | FileCheck %s
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target datalayout = "E-m:e-i64:64-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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; Function Attrs: nounwind readonly
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define double @test1(i64* nocapture readonly %x) #0 {
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entry:
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%0 = load i64* %x, align 8
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%conv = sitofp i64 %0 to double
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ret double %conv
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; CHECK-LABEL: @test1
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; CHECK: lfd [[REG1:[0-9]+]], 0(3)
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; CHECK: fcfid 1, [[REG1]]
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; CHECK: blr
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}
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; Function Attrs: nounwind readonly
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define double @test2(i32* nocapture readonly %x) #0 {
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entry:
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%0 = load i32* %x, align 4
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%conv = sitofp i32 %0 to double
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ret double %conv
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; CHECK-LABEL: @test2
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; CHECK: lfiwax [[REG1:[0-9]+]], 0, 3
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; CHECK: fcfid 1, [[REG1]]
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; CHECK: blr
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}
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; Function Attrs: nounwind readnone
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define float @foo(float %X) #0 {
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entry:
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%conv = fptosi float %X to i32
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%conv1 = sitofp i32 %conv to float
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ret float %conv1
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; CHECK-LABEL: @foo
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; CHECK-DAG: fctiwz [[REG2:[0-9]+]], 1
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; CHECK-DAG: addi [[REG1:[0-9]+]], 1,
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; CHECK: stfiwx [[REG2]], 0, [[REG1]]
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; CHECK: lfiwax [[REG3:[0-9]+]], 0, [[REG1]]
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; CHECK: fcfids 1, [[REG3]]
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; CHECK: blr
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}
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; Function Attrs: nounwind readnone
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define double @food(double %X) #0 {
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entry:
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%conv = fptosi double %X to i32
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%conv1 = sitofp i32 %conv to double
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ret double %conv1
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; CHECK-LABEL: @food
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; CHECK-DAG: fctiwz [[REG2:[0-9]+]], 1
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; CHECK-DAG: addi [[REG1:[0-9]+]], 1,
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; CHECK: stfiwx [[REG2]], 0, [[REG1]]
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; CHECK: lfiwax [[REG3:[0-9]+]], 0, [[REG1]]
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; CHECK: fcfid 1, [[REG3]]
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; CHECK: blr
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}
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; Function Attrs: nounwind readnone
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define float @foou(float %X) #0 {
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entry:
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%conv = fptoui float %X to i32
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%conv1 = uitofp i32 %conv to float
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ret float %conv1
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; CHECK-LABEL: @foou
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; CHECK-DAG: fctiwuz [[REG2:[0-9]+]], 1
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; CHECK-DAG: addi [[REG1:[0-9]+]], 1,
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; CHECK: stfiwx [[REG2]], 0, [[REG1]]
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; CHECK: lfiwzx [[REG3:[0-9]+]], 0, [[REG1]]
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; CHECK: fcfidus 1, [[REG3]]
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; CHECK: blr
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}
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; Function Attrs: nounwind readnone
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define double @fooud(double %X) #0 {
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entry:
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%conv = fptoui double %X to i32
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%conv1 = uitofp i32 %conv to double
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ret double %conv1
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; CHECK-LABEL: @fooud
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; CHECK-DAG: fctiwuz [[REG2:[0-9]+]], 1
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; CHECK-DAG: addi [[REG1:[0-9]+]], 1,
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; CHECK: stfiwx [[REG2]], 0, [[REG1]]
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; CHECK: lfiwzx [[REG3:[0-9]+]], 0, [[REG1]]
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; CHECK: fcfidu 1, [[REG3]]
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; CHECK: blr
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}
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attributes #0 = { nounwind readonly }
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