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Sub-register lane masks are bitmasks that can be used to determine if two sub-registers of a virtual register will overlap. For example, ARM's ssub0 and ssub1 sub-register indices don't overlap each other, but both overlap dsub0 and qsub0. The lane masks will be accurate on most targets, but on targets that use sub-register indexes in an irregular way, the masks may conservatively report that two sub-register indices overlap when the eventually allocated physregs don't. Irregular register banks also mean that the bits in a lane mask can't be mapped onto register units, but the concept is similar. llvm-svn: 163630 |
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