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Support for 64-bit coprocessors on a 32-bit architecture was added in `MIPS32 R2`. llvm-svn: 365507
42 lines
1.8 KiB
LLVM
42 lines
1.8 KiB
LLVM
; Test that the compiled does not fuse fmul and fadd into fmadd when no -fp-contract=fast
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; option is set (the same applies for fmul, fsub and fmsub).
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; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s \
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; RUN: | FileCheck %s --check-prefixes=CHECK-CONTRACT-OFF
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; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -fp-contract=off < %s \
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; RUN: | FileCheck %s --check-prefixes=CHECK-CONTRACT-OFF
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; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -fp-contract=fast < %s \
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; RUN: | FileCheck %s --check-prefixes=CHECK-CONTRACT-FAST
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declare <4 x float> @llvm.mips.fmul.w(<4 x float>, <4 x float>)
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declare <4 x float> @llvm.mips.fadd.w(<4 x float>, <4 x float>)
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declare <4 x float> @llvm.mips.fsub.w(<4 x float>, <4 x float>)
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define void @foo(<4 x float>* %agg.result, <4 x float>* %acc, <4 x float>* %a, <4 x float>* %b) {
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entry:
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%0 = load <4 x float>, <4 x float>* %a, align 16
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%1 = load <4 x float>, <4 x float>* %b, align 16
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%2 = call <4 x float> @llvm.mips.fmul.w(<4 x float> %0, <4 x float> %1)
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%3 = load <4 x float>, <4 x float>* %acc, align 16
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%4 = call <4 x float> @llvm.mips.fadd.w(<4 x float> %3, <4 x float> %2)
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store <4 x float> %4, <4 x float>* %agg.result, align 16
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ret void
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; CHECK-CONTRACT-OFF: fmul.w
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; CHECK-CONTRACT-OFF: fadd.w
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; CHECK-CONTRACT-FAST: fmadd.w
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}
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define void @boo(<4 x float>* %agg.result, <4 x float>* %acc, <4 x float>* %a, <4 x float>* %b) {
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entry:
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%0 = load <4 x float>, <4 x float>* %a, align 16
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%1 = load <4 x float>, <4 x float>* %b, align 16
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%2 = call <4 x float> @llvm.mips.fmul.w(<4 x float> %0, <4 x float> %1)
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%3 = load <4 x float>, <4 x float>* %acc, align 16
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%4 = call <4 x float> @llvm.mips.fsub.w(<4 x float> %3, <4 x float> %2)
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store <4 x float> %4, <4 x float>* %agg.result, align 16
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ret void
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; CHECK-CONTRACT-OFF: fmul.w
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; CHECK-CONTRACT-OFF: fsub.w
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; CHECK-CONTRACT-FAST: fmsub.w
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}
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