Craig Topper fa61017019 [SelectionDAG][RISCV] Use isSExtCheaperThanZExt to control whether sext or zext is used for constant folding any_extend. ... RISCV would prefer a sign extended constant since that works better with our constant materialization. We have an existing TLI hook we use to control sign extension of setcc operands in type legalization. That hook happens to do the right check we need here, but might be straying from its original purpose. With only RISCV defining this hook in tree, I wasn't sure if it was worth adding another hook with identical behavior. This is an alternative to D105785 where I tried to handle this in the RISCV backend by not creating ANY_EXTENDs in some places. Reviewed By: frasercrmck Differential Revision: https://reviews.llvm.org/D105918		2021-07-19 09:25:28 -07:00
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AArch64	[AArch64][SVE] Optimize bitcasts between unpacked half/i16 vectors.	2021-07-19 08:29:28 +01:00
AMDGPU	GlobalISel: Preserve memory types for implicit sret load/stores	2021-07-19 11:52:42 -04:00
ARC
ARM	[ARM] Remove PromotedBitwiseVT for NEON types	2021-07-19 16:36:33 +01:00
AVR
BPF	[BPF] Use elementtype attribute for preserve.array/struct.index intrinsics	2021-07-17 11:09:18 +02:00
Generic
Hexagon
Inputs
Lanai
M68k
Mips
MIR
MSP430
NVPTX	[NVPTX] Add select(cc,binop(),binop()) fast-math tests	2021-07-18 15:30:24 +01:00
PowerPC	[PowerPC] Implement intrinsics for mtfsf[i]	2021-07-16 16:26:11 -05:00
RISCV	[SelectionDAG][RISCV] Use isSExtCheaperThanZExt to control whether sext or zext is used for constant folding any_extend.	2021-07-19 09:25:28 -07:00
SPARC
SystemZ
Thumb
Thumb2	[ARM] Extend more reductions during lowering	2021-07-19 08:58:03 +01:00
VE
WebAssembly
WinCFGuard
WinEH
X86	[TLI] prepareSREMEqFold(): use correct VT for the final VSELECT (PR51133)	2021-07-19 16:44:00 +03:00
XCore