Serge Pavlov b8ce9ec478 Add extra operand to CALLSEQ_START to keep frame part set up previously ... Using arguments with attribute inalloca creates problems for verification of machine representation. This attribute instructs the backend that the argument is prepared in stack prior to CALLSEQ_START..CALLSEQ_END sequence (see http://llvm.org/docs/InAlloca.htm for details). Frame size stored in CALLSEQ_START in this case does not count the size of this argument. However CALLSEQ_END still keeps total frame size, as caller can be responsible for cleanup of entire frame. So CALLSEQ_START and CALLSEQ_END keep different frame size and the difference is treated by MachineVerifier as stack error. Currently there is no way to distinguish this case from actual errors. This patch adds additional argument to CALLSEQ_START and its target-specific counterparts to keep size of stack that is set up prior to the call frame sequence. This argument allows MachineVerifier to calculate actual frame size associated with frame setup instruction and correctly process the case of inalloca arguments. The changes made by the patch are: - Frame setup instructions get the second mandatory argument. It affects all targets that use frame pseudo instructions and touched many files although the changes are uniform. - Access to frame properties are implemented using special instructions rather than calls getOperand(N).getImm(). For X86 and ARM such replacement was made previously. - Changes that reflect appearance of additional argument of frame setup instruction. These involve proper instruction initialization and methods that access instruction arguments. - MachineVerifier retrieves frame size using method, which reports sum of frame parts initialized inside frame instruction pair and outside it. The patch implements approach proposed by Quentin Colombet in https://bugs.llvm.org/show_bug.cgi?id=27481#c1. It fixes 9 tests failed with machine verifier enabled and listed in PR27481. Differential Revision: https://reviews.llvm.org/D32394 llvm-svn: 302527		2017-05-09 13:35:13 +00:00
..
intrinsics	[Hexagon] Add intrinsics for masked vector stores	2017-02-22 21:23:09 +00:00
loop-idiom	[Hexagon] Avoid infinite loops in HexagonLoopIdiomRecognition	2017-03-23 23:01:22 +00:00
vect	[Hexagon] Generate extract instructions more aggressively	2017-02-28 23:27:33 +00:00
absaddr-store.ll
absimm.ll
adde.ll	[Hexagon] Propagate zext of i1 into arithmetic code in selection DAG	2017-03-09 16:29:30 +00:00
addh-sext-trunc.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
addh-shifted.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
addh.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
addr-calc-opt.ll
addrmode-globoff.mir	[Hexagon] Generate proper offset in opt-addr-mode	2017-04-19 15:15:51 +00:00
addrmode-indoff.ll
adjust-latency-stackST.ll	[Hexagon] Adjust latency between allocframe and the first store on stack	2017-05-03 15:33:09 +00:00
alu64.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
always-ext.ll
anti-dep-partial.mir	Move .mir tests to appropriate directories	2016-12-09 19:08:15 +00:00
args.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
ashift-left-right.ll
Atomics.ll
avoid-predspill-calleesaved.ll	[Hexagon] Start using regmasks on calls	2017-02-17 22:14:51 +00:00
avoid-predspill.ll
barrier-flag.ll
base-offset-addr.ll
base-offset-post.ll
bit-bitsplit-at.ll	[Hexagon] Fixes to the bitsplit generation	2017-03-09 22:02:14 +00:00
bit-bitsplit-src.ll	[Hexagon] Generate bitsplit instruction	2017-03-07 23:08:35 +00:00
bit-bitsplit.ll	[Hexagon] Generate bitsplit instruction	2017-03-07 23:08:35 +00:00
bit-eval.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
bit-ext-sat.ll	[Hexagon] Handle saturations in Hexagon bit tracker	2017-02-23 22:11:52 +00:00
bit-extract-off.ll	[Hexagon] Use correct offset when extracting from the high word	2017-03-08 15:46:28 +00:00
bit-extract.ll	[Hexagon] Generate extract instructions more aggressively	2017-02-28 23:27:33 +00:00
bit-extractu-half.ll
bit-gen-rseq.ll
bit-has.ll	[Hexagon] Check for presence before looking registers up in bit tracker	2017-03-07 23:12:04 +00:00
bit-loop-rc-mismatch.ll
bit-loop.ll
bit-phi.ll	[Hexagon] Do not insert instructions before PHI nodes	2017-03-07 14:20:19 +00:00
bit-rie.ll	Add address space mangling to lifetime intrinsics	2017-04-10 20:18:21 +00:00
bit-skip-byval.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
bit-validate-reg.ll	[Hexagon] Generate extract instructions more aggressively	2017-02-28 23:27:33 +00:00
bit-visit-flowq.ll
bitconvert-vector.ll
bitmanip.ll	[Hexagon] Patterns for CTPOP, BSWAP and BITREVERSE	2017-02-23 15:02:09 +00:00
block-addr.ll	[Hexagon] Early-if-convert branches that may exit the loop	2017-03-06 17:24:04 +00:00
block-ranges-nodef.ll
branch-folder-hoist-kills.mir	Remove stale live-ins in the branch folder	2017-05-05 12:20:07 +00:00
branch-non-mbb.ll
branchfolder-keep-impdef.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
BranchPredict.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
brev_ld.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
brev_st.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
bugAsmHWloop.ll
build-vector-shuffle.ll
builtin-expect.ll	[Hexagon] Pick the right branch opcode depending on branch probabilities	2017-03-02 21:49:49 +00:00
builtin-prefetch-offset.ll
builtin-prefetch.ll
calling-conv-2.ll
callr-dep-edge.ll
cext-check.ll
cext-valid-packet1.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
cext-valid-packet2.ll
cext.ll
cexti16.ll
cfgopt-fall-through.ll	[Hexagon] Do not move a block if it is on a fall-through path	2017-04-28 21:54:11 +00:00
cfi-late.ll
cfi-offset.ll
checktabs.ll
circ_ld.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
circ_ldd_bug.ll
circ_ldw.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
circ_st.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
circ-load-isel.ll
clr_set_toggle.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
cmp_pred2.ll
cmp_pred_reg.ll
cmp_pred.ll
cmp-extend.ll
cmp-promote.ll
cmp-to-genreg.ll
cmp-to-predreg.ll
cmp.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
cmpb_pred.ll
cmpb-eq.ll
combine_ir.ll
combine.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
common-gep-basic.ll
common-gep-icm.ll
compound.ll	[Hexagon] Start using regmasks on calls	2017-02-17 22:14:51 +00:00
const64.ll
const-pool-tf.ll
constp-clb.ll
constp-combine-neg.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
constp-ctb.ll
constp-extract.ll
constp-physreg.ll
constp-rewrite-branches.ll
constp-rseq.ll
constp-vsplat.ll
convert-to-dot-old.ll	[Hexagon] Pick a dot-old instruction that matches the architecture	2017-03-06 17:03:16 +00:00
convertdptoint.ll
convertdptoll.ll
convertsptoint.ll
convertsptoll.ll
copy-to-combine-dbg.ll
csr-func-usedef.ll
ctor.ll
dadd.ll
dead-store-stack.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
dmul.ll
double.ll
doubleconvert-ieee-rnd-near.ll
dsub.ll
dualstore.ll
duplex.ll
early-if-conversion-bug1.ll
early-if-merge-loop.ll	[Hexagon] Early-if-convert branches that may exit the loop	2017-03-06 17:24:04 +00:00
early-if-phi-i1.ll	[Hexagon] Add -march=hexagon to a testcase	2017-03-21 16:59:40 +00:00
early-if-spare.ll
early-if-vecpi.ll
early-if-vecpred.ll	[Hexagon] Skip blocks that define vector predicate registers in early-if	2017-03-02 18:10:59 +00:00
early-if.ll
eh_return.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
eliminate-pred-spill.ll	[Hexagon] Use -mattr to select HVX mode in a testcase, NFC	2017-04-05 19:46:37 +00:00
expand-condsets-basic.ll
expand-condsets-dead-bad.ll	[Hexagon] Mark dead defs as <dead> in expand-condsets	2017-03-06 17:09:06 +00:00
expand-condsets-dead-pred.ll	[Hexagon] Mark dead defs as <dead> in expand-condsets	2017-03-06 17:09:06 +00:00
expand-condsets-def-undef.mir	[Hexagon] Separate Hexagon subreg indices for different register classes	2016-11-09 16:19:08 +00:00
expand-condsets-extend.ll
expand-condsets-impuse.mir	[Hexagon] Maintain kill flags through splitting in expand-condsets	2016-10-28 15:50:22 +00:00
expand-condsets-pred-undef.ll
expand-condsets-rm-reg.mir	Bring back 2>&1 redirection for this test	2017-02-22 19:16:33 +00:00
expand-condsets-rm-segment.ll
expand-condsets-same-inputs.mir	[Hexagon] Don't expand mux instructions with both sources identical	2016-10-31 15:45:09 +00:00
expand-condsets-undef2.ll
expand-condsets-undef.ll
expand-vstorerw-undef2.ll	[Hexagon] Remove dead defs from the live set when expanding wstores	2017-01-18 23:11:40 +00:00
expand-vstorerw-undef.ll
extload-combine.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
extract-basic.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
fadd.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
fcmp.ll
find-loop-instr.ll	[Hexagon] Fix insertBranch for loops with multiple ENDLOOP instructions	2017-02-02 19:36:37 +00:00
fixed-spill-mutable.ll
float-amode.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
float.ll
floatconvert-ieee-rnd-near.ll
fminmax.ll
fmul.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
frame-offset-overflow.ll
frame.ll
fsel.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
fsub.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
fusedandshift.ll	[Hexagon] Generate extract instructions more aggressively	2017-02-28 23:27:33 +00:00
gp-plus-offset-load.ll
gp-plus-offset-store.ll
gp-rel.ll	[Hexagon] Adding gp+ to the syntax of gp-relative instructions	2017-02-06 23:18:57 +00:00
hwloop1.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
hwloop2.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
hwloop3.ll
hwloop4.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
hwloop5.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
hwloop-cleanup.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
hwloop-const.ll
hwloop-crit-edge.ll
hwloop-dbg.ll
hwloop-le.ll
hwloop-loop1.ll	Add address space mangling to lifetime intrinsics	2017-04-10 20:18:21 +00:00
hwloop-lt1.ll
hwloop-lt.ll
hwloop-missed.ll
hwloop-ne.ll
hwloop-noreturn-call.ll
hwloop-ph-deadcode.ll
hwloop-pos-ivbump1.ll
hwloop-preh.ll
hwloop-preheader.ll
hwloop-range.ll
hwloop-recursion.ll
hwloop-wrap2.ll
hwloop-wrap.ll
i1_VarArg.ll
i8_VarArg.ll
i16_VarArg.ll
idxload-with-zero-offset.ll
ifcvt-diamond-bad.ll
ifcvt-diamond-bug-2016-08-26.ll	[Hexagon] Fix typo in HexagonEarlyIfCConv.cpp	2017-03-31 20:36:00 +00:00
ifcvt-edge-weight.ll
ifcvt-impuse-livein.mir
ifcvt-live-subreg.mir
ifcvt-simple-bprob.ll	[IfConversion] Only renormalize probabilities if branches are analyzable	2017-03-06 19:12:42 +00:00
indirect-br.ll
inline-asm-hexagon.ll
inline-asm-i1.ll
inline-asm-qv.ll
inline-asm-vecpred128.ll	[Hexagon] Properly handle 'q' constraint in 128-byte vector mode	2017-03-02 17:50:24 +00:00
insert4.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
insert-basic.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
is-legal-void.ll
isel-exti1.ll	[Hexagon] Fix instruction selection for sign-extending i1 to i64	2017-02-28 22:37:01 +00:00
isel-i1arg-crash.ll	[Hexagon] Fix lowering of formal arguments of type i1	2017-03-01 17:30:10 +00:00
isel-op-zext-i1.ll	[Hexagon] Propagate zext of i1 into arithmetic code in selection DAG	2017-03-09 16:29:30 +00:00
lit.local.cfg
livephysregs-lane-masks2.mir	Handle non-~0 lane masks on live-in registers in LivePhysRegs	2016-10-28 20:06:37 +00:00
livephysregs-lane-masks.mir
loadi1-G0.ll
loadi1-v4-G0.ll
loadi1-v4.ll
loadi1.ll
long-calls.ll
loop-prefetch.ll
lower-extract-subvector.ll
macint.ll
maxd.ll
maxh.ll
maxud.ll
maxuw.ll
maxw.ll
mem-fi-add.ll
memcpy-likely-aligned.ll
memops1.ll
memops2.ll
memops3.ll
memops-stack.ll	Add address space mangling to lifetime intrinsics	2017-04-10 20:18:21 +00:00
memops.ll
mind.ll
minu-zext-8.ll
minu-zext-16.ll
minud.ll
minuw.ll
minw.ll
misaligned_double_vector_store_not_fast.ll
misaligned-access.ll
misched-top-rptracker-sync.ll
mpy.ll
mulhs.ll
multi-cycle.ll	[Hexagon] Don't ignore mult-cycle latency information	2017-05-02 18:12:19 +00:00
mux-basic.ll
newvaluejump2.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
newvaluejump3.ll	[Hexagon] Avoid IMPLICIT_DEFs as new-value producers	2017-02-23 17:47:34 +00:00
newvaluejump.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
newvalueSameReg.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
newvaluestore.ll
NVJumpCmp.ll
opt-addr-mode.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
opt-fabs.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
opt-fneg.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
opt-spill-volatile.ll	Add address space mangling to lifetime intrinsics	2017-04-10 20:18:21 +00:00
packetize_cond_inst.ll
packetize-cfi-location.ll
packetize-return-arg.ll
packetize-tailcall-arg.ll
peephole-kill-flags.ll
peephole-op-swap.ll
pic-jumptables.ll
pic-local.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
pic-regusage.ll
pic-simple.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
pic-static.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
plt-rel.ll	[Hexagon] Add extenders for GD_PLT_B22_PCREL and LD_PLT_B22_PCREL	2017-05-02 18:15:33 +00:00
post-inc-aa-metadata.ll
post-ra-kill-update.mir
postinc-load.ll
postinc-offset.ll
postinc-store.ll
pred-absolute-store.ll	[RDF] Remove the map of reaching defs from copy propagation	2017-03-10 22:44:24 +00:00
pred-gp.ll
pred-instrs.ll
predicate-copy.ll
predicate-logical.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
predicate-rcmp.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
propagate-vcombine.ll
rdf-copy-undef2.ll	Add address space mangling to lifetime intrinsics	2017-04-10 20:18:21 +00:00
rdf-copy.ll
rdf-cover-use.ll	[RDF] Remove covered parts of reached uses for phi and use in same block	2017-05-05 22:10:32 +00:00
rdf-dead-loop.ll
rdf-def-mask.ll	[RDF] Correctly calculate lane masks for defs	2017-04-28 21:57:53 +00:00
rdf-extra-livein.ll
rdf-filter-defs.ll
rdf-ignore-undef.ll
rdf-inline-asm-fixed.ll	Add address space mangling to lifetime intrinsics	2017-04-10 20:18:21 +00:00
rdf-inline-asm.ll
rdf-multiple-phis-up.ll
rdf-phi-shadows.ll
rdf-phi-up.ll	Add address space mangling to lifetime intrinsics	2017-04-10 20:18:21 +00:00
rdf-reset-kills.ll
readcyclecounter.ll	[Hexagon] Implement @llvm.readcyclecounter()	2017-02-22 22:28:47 +00:00
reg-scavengebug-3.ll
reg-scavenger-valid-slot.ll
regalloc-bad-undef.mir	Add extra operand to CALLSEQ_START to keep frame part set up previously	2017-05-09 13:35:13 +00:00
regalloc-block-overlap.ll	Treat segment [B, E) as not overlapping block with boundaries [A, B)	2017-01-18 23:12:19 +00:00
relax.ll
remove_lsr.ll
remove-endloop.ll
restore-single-reg.ll
ret-struct-by-val.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
runtime-stkchk.ll	Add address space mangling to lifetime intrinsics	2017-04-10 20:18:21 +00:00
sdata-array.ll
sdata-basic.ll
sdr-basic.ll
sdr-shr32.ll
section_7275.ll	[Hexagon] Adding gp+ to the syntax of gp-relative instructions	2017-02-06 23:18:57 +00:00
select-instr-align.ll
sf-min-max.ll
sffms.ll
shrink-frame-basic.ll
signed_immediates.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
simple_addend.ll
simpletailcall.ll
split-const32-const64.ll
stack-align1.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
stack-align2.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
stack-alloca1.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
stack-alloca2.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
static.ll	[Hexagon] Adding gp+ to the syntax of gp-relative instructions	2017-02-06 23:18:57 +00:00
store-shift.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
store-widen-aliased-load.ll
store-widen-negv2.ll
store-widen-negv.ll
store-widen.ll
storerd-io-over-rr.ll
storerinewabs.ll
struct_args_large.ll
struct_args.ll
sube.ll	[Hexagon] Propagate zext of i1 into arithmetic code in selection DAG	2017-03-09 16:29:30 +00:00
subi-asl.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
SUnit-boundary-prob.ll
swp-const-tc.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
swp-dag-phi.ll
swp-epilog-phi10.ll	Fix two bugs in the pipeliner in renaming phis in the prolog and epilog	2016-12-22 18:49:55 +00:00
swp-epilog-reuse-1.ll
swp-epilog-reuse.ll
swp-matmul-bitext.ll	[Hexagon] Use automatically-generated scheduling information for HVX	2017-05-03 20:10:36 +00:00
swp-max.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
swp-multi-loops.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
swp-prolog-phi4.ll	Fix two bugs in the pipeliner in renaming phis in the prolog and epilog	2016-12-22 18:49:55 +00:00
swp-stages4.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
swp-stages5.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
swp-vect-dotprod.ll
swp-vmult.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
swp-vsum.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
tail-call-mem-intrinsics.ll
tail-call-trunc.ll
tail-dup-subreg-abort.ll
tail-dup-subreg-map.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
tailcall_fastcc_ccc.ll
tfr-to-combine.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
tls_pic.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
tls_static.ll
two-crash.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
undo-dag-shift.ll	[Hexagon] Undo shift folding where it could simplify addressing mode	2017-02-24 23:34:24 +00:00
union-1.ll
unreachable-mbb-phi-subreg.mir	Properly handle PHIs with subregisters in UnreachableBlockElim	2017-04-28 21:56:33 +00:00
usr-ovf-dep.ll
v6vec-vprint.ll
v60-cur.ll
v60-vsel1.ll	[Hexagon] Do not expand ISD::SELECT for HVX vectors	2016-10-27 14:30:16 +00:00
v60Intrins.ll
v60small.ll
v60Vasr.ll
vaddh.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
validate-offset.ll
vassign-to-combine.ll
vdmpy-halide-test.ll
vec-pred-spill1.ll
vector-align.ll
vector-ext-load.ll
vload-postinc-sel.ll
vmpa-halide-test.ll
vpack_eo.ll
vselect-pseudo.ll
vsplat-isel.ll
zextloadi1.ll