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50 lines
1.2 KiB
LLVM
50 lines
1.2 KiB
LLVM
; RUN: llc -march=hexagon -hexagon-small-data-threshold=0 < %s | FileCheck %s
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; Check that we generate load instructions with absolute addressing mode.
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@a0 = external global i32
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@a1 = external global i32
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@b0 = external global i8
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@b1 = external global i8
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@c0 = external global i16
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@c1 = external global i16
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@d = external global i64
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define zeroext i8 @absStoreByte() nounwind {
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; CHECK: memb(##b1){{ *}}={{ *}}r{{[0-9]+}}
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entry:
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%0 = load i8, i8* @b0, align 1
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%conv = zext i8 %0 to i32
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%mul = mul nsw i32 100, %conv
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%conv1 = trunc i32 %mul to i8
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store i8 %conv1, i8* @b1, align 1
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ret i8 %conv1
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}
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define signext i16 @absStoreHalf() nounwind {
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; CHECK: memh(##c1){{ *}}={{ *}}r{{[0-9]+}}
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entry:
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%0 = load i16, i16* @c0, align 2
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%conv = sext i16 %0 to i32
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%mul = mul nsw i32 100, %conv
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%conv1 = trunc i32 %mul to i16
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store i16 %conv1, i16* @c1, align 2
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ret i16 %conv1
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}
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define i32 @absStoreWord() nounwind {
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; CHECK: memw(##a1){{ *}}={{ *}}r{{[0-9]+}}
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entry:
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%0 = load i32, i32* @a0, align 4
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%mul = mul nsw i32 100, %0
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store i32 %mul, i32* @a1, align 4
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ret i32 %mul
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}
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define void @absStoreDouble() nounwind {
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; CHECK: memd(##d){{ *}}={{ *}}r{{[0-9]+}}:{{[0-9]+}}
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entry:
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store i64 100, i64* @d, align 8
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ret void
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}
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