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llvm-mirror/test/CodeGen/Thumb
Nirav Dave 3633380341 Elide stores which are overwritten without being observed.
Summary:
In SelectionDAG, when a store is immediately chained to another store
to the same address, elide the first store as it has no observable
effects. This is causes small improvements dealing with intrinsics
lowered to stores.

Test notes:

* Many testcases overwrite store addresses multiple times and needed
  minor changes, mainly making stores volatile to prevent the
  optimization from optimizing the test away.

* Many X86 test cases optimized out instructions associated with
  associated with va_start.

* Note that test_splat in CodeGen/AArch64/misched-stp.ll no longer has
  dependencies to check and can probably be removed and potentially
  replaced with another test.

Reviewers: rnk, john.brawn

Subscribers: aemerson, rengolin, qcolombet, jyknight, nemanjai, nhaehnle, javed.absar, llvm-commits

Differential Revision: https://reviews.llvm.org/D33206

llvm-svn: 303198
2017-05-16 19:43:56 +00:00
..
2007-01-31-RegInfoAssert.ll
2007-02-02-JoinIntervalsCrash.ll
2007-05-05-InvalidPushPop.ll
2009-06-18-ThumbCommuteMul.ll
2009-07-20-TwoAddrBug.ll
2009-07-27-PEIAssert.ll
2009-08-12-ConstIslandAssert.ll
2009-08-12-RegInfoAssert.ll
2009-08-20-ISelBug.ll
2009-12-17-pre-regalloc-taildup.ll
2010-06-18-SibCallCrash.ll
2010-07-01-FuncAlign.ll
2010-07-15-debugOrdering.ll In visitSTORE, always use FindBetterChain, rather than only when UseAA is enabled. 2017-03-14 00:34:14 +00:00
2011-05-11-DAGLegalizer.ll
2011-06-16-NoGPRs.ll
2011-EpilogueBug.ll
2012-04-26-M0ISelBug.ll
2014-06-10-thumb1-ldst-opt-bug.ll
and_neg.ll
asmprinter-bug.ll
barrier.ll
bic_imm.ll
callee_save.ll Re-land "[Thumb] Save/restore high registers in Thumb1 pro/epilogues" 2016-10-11 21:14:03 +00:00
cmp-add-fold.ll In Thumb1 mode, the custom lowering for ARMISD::CMPZ could never emit tADDi3 2017-02-17 18:59:16 +00:00
cmp-fold.ll
constants.ll
copy_thumb.ll In Thumb1, materialize a move between low registers as a movs, if CPSR isn't live. 2017-03-07 09:38:16 +00:00
cortex-m0-unaligned-access.ll
DbgValueOtherTargets.test
dyn-stackalloc.ll
fastcc.ll
fpconv.ll
fpow.ll
frame_thumb.ll
iabs.ll
inlineasm-imm-thumb.ll
inlineasm-thumb.ll
ispositive.ll [ARM] t2_so_imm_neg had a subtle bug in the conversion, and could trigger UB by negating (int)-2147483648. By pure luck, none of the pre-existing tests triggered this; so I'm adding one. 2017-03-22 15:09:30 +00:00
large-stack.ll Re-land "[Thumb] Save/restore high registers in Thumb1 pro/epilogues" 2016-10-11 21:14:03 +00:00
ldm-merge-call.ll
ldm-merge-struct.ll
ldm-stm-base-materialization-thumb2.ll
ldm-stm-base-materialization.ll
ldm-stm-postinc.ll
ldr_ext.ll
ldr_frame.ll
lit.local.cfg
long_shift.ll
long-setcc.ll
long.ll [Thumb1] The recently added tADCS and tSBCS pseudo-instructions were missing Uses = [CPSR] 2017-04-21 07:35:21 +00:00
mature-mc-support.ll [LLC] Add an inline assembly diagnostics handler. 2017-02-03 11:14:39 +00:00
mul.ll
optionaldef-scheduling.ll [ARM] ScheduleDAGRRList::DelayForLiveRegsBottomUp must consider OptionalDefs 2017-04-23 06:58:08 +00:00
pop.ll
PR17309.ll Add address space mangling to lifetime intrinsics 2017-04-10 20:18:21 +00:00
push.ll
remove-unneeded-push-pop.ll [ARM] Fix constant islands pass. 2017-02-22 09:06:21 +00:00
rev.ll
segmented-stacks-dynamic.ll
segmented-stacks.ll
select.ll
sjljehprepare-lower-vector.ll
stack_guard_remat.ll Add address space mangling to lifetime intrinsics 2017-04-10 20:18:21 +00:00
stack-access.ll Elide stores which are overwritten without being observed. 2017-05-16 19:43:56 +00:00
stack-coloring-without-frame-ptr.ll Add address space mangling to lifetime intrinsics 2017-04-10 20:18:21 +00:00
stack-frame.ll
stm-deprecated.ll [ARM] Don't generate deprecated T1 STM. 2017-02-28 23:32:55 +00:00
stm-merge.ll
tbb-reuse.mir [Thumb-1] TBB generation: spot redefinitions of index register 2017-02-13 14:07:39 +00:00
thumb-imm.ll
thumb-ldm.ll
thumb-shrink-wrapping.ll In Thumb1, materialize a move between low registers as a movs, if CPSR isn't live. 2017-03-07 09:38:16 +00:00
trap.ll
triple.ll
tst_teq.ll
unord.ll
vargs.ll