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https://github.com/RPCS3/llvm-mirror.git
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fd1cb2ca1c
This is a cleanup/rewrite of the parseSysAlias function. It was not using the tablegen instruction descriptions, but was “manually” matching the mnemonics and recreating the operands whereas all this information is already in tablegen; all this code has been replaced with calls to lookupXYZByName tablegen calls. Differential Revision: https://reviews.llvm.org/D30491 llvm-svn: 296857
527 lines
17 KiB
C++
527 lines
17 KiB
C++
//===-- AArch64BaseInfo.h - Top level definitions for AArch64 ---*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains small standalone helper functions and enum definitions for
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// the AArch64 target useful for the compiler back-end and the MC libraries.
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// As such, it deliberately does not include references to LLVM core
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// code gen types, passes, etc..
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AARCH64_UTILS_AARCH64BASEINFO_H
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#define LLVM_LIB_TARGET_AARCH64_UTILS_AARCH64BASEINFO_H
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// FIXME: Is it easiest to fix this layering violation by moving the .inc
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// #includes from AArch64MCTargetDesc.h to here?
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#include "MCTargetDesc/AArch64MCTargetDesc.h" // For AArch64::X0 and friends.
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/StringSwitch.h"
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#include "llvm/MC/SubtargetFeature.h"
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#include "llvm/Support/ErrorHandling.h"
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namespace llvm {
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inline static unsigned getWRegFromXReg(unsigned Reg) {
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switch (Reg) {
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case AArch64::X0: return AArch64::W0;
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case AArch64::X1: return AArch64::W1;
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case AArch64::X2: return AArch64::W2;
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case AArch64::X3: return AArch64::W3;
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case AArch64::X4: return AArch64::W4;
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case AArch64::X5: return AArch64::W5;
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case AArch64::X6: return AArch64::W6;
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case AArch64::X7: return AArch64::W7;
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case AArch64::X8: return AArch64::W8;
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case AArch64::X9: return AArch64::W9;
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case AArch64::X10: return AArch64::W10;
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case AArch64::X11: return AArch64::W11;
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case AArch64::X12: return AArch64::W12;
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case AArch64::X13: return AArch64::W13;
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case AArch64::X14: return AArch64::W14;
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case AArch64::X15: return AArch64::W15;
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case AArch64::X16: return AArch64::W16;
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case AArch64::X17: return AArch64::W17;
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case AArch64::X18: return AArch64::W18;
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case AArch64::X19: return AArch64::W19;
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case AArch64::X20: return AArch64::W20;
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case AArch64::X21: return AArch64::W21;
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case AArch64::X22: return AArch64::W22;
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case AArch64::X23: return AArch64::W23;
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case AArch64::X24: return AArch64::W24;
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case AArch64::X25: return AArch64::W25;
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case AArch64::X26: return AArch64::W26;
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case AArch64::X27: return AArch64::W27;
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case AArch64::X28: return AArch64::W28;
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case AArch64::FP: return AArch64::W29;
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case AArch64::LR: return AArch64::W30;
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case AArch64::SP: return AArch64::WSP;
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case AArch64::XZR: return AArch64::WZR;
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}
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// For anything else, return it unchanged.
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return Reg;
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}
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inline static unsigned getXRegFromWReg(unsigned Reg) {
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switch (Reg) {
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case AArch64::W0: return AArch64::X0;
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case AArch64::W1: return AArch64::X1;
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case AArch64::W2: return AArch64::X2;
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case AArch64::W3: return AArch64::X3;
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case AArch64::W4: return AArch64::X4;
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case AArch64::W5: return AArch64::X5;
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case AArch64::W6: return AArch64::X6;
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case AArch64::W7: return AArch64::X7;
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case AArch64::W8: return AArch64::X8;
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case AArch64::W9: return AArch64::X9;
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case AArch64::W10: return AArch64::X10;
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case AArch64::W11: return AArch64::X11;
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case AArch64::W12: return AArch64::X12;
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case AArch64::W13: return AArch64::X13;
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case AArch64::W14: return AArch64::X14;
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case AArch64::W15: return AArch64::X15;
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case AArch64::W16: return AArch64::X16;
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case AArch64::W17: return AArch64::X17;
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case AArch64::W18: return AArch64::X18;
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case AArch64::W19: return AArch64::X19;
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case AArch64::W20: return AArch64::X20;
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case AArch64::W21: return AArch64::X21;
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case AArch64::W22: return AArch64::X22;
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case AArch64::W23: return AArch64::X23;
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case AArch64::W24: return AArch64::X24;
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case AArch64::W25: return AArch64::X25;
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case AArch64::W26: return AArch64::X26;
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case AArch64::W27: return AArch64::X27;
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case AArch64::W28: return AArch64::X28;
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case AArch64::W29: return AArch64::FP;
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case AArch64::W30: return AArch64::LR;
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case AArch64::WSP: return AArch64::SP;
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case AArch64::WZR: return AArch64::XZR;
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}
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// For anything else, return it unchanged.
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return Reg;
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}
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static inline unsigned getBRegFromDReg(unsigned Reg) {
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switch (Reg) {
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case AArch64::D0: return AArch64::B0;
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case AArch64::D1: return AArch64::B1;
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case AArch64::D2: return AArch64::B2;
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case AArch64::D3: return AArch64::B3;
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case AArch64::D4: return AArch64::B4;
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case AArch64::D5: return AArch64::B5;
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case AArch64::D6: return AArch64::B6;
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case AArch64::D7: return AArch64::B7;
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case AArch64::D8: return AArch64::B8;
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case AArch64::D9: return AArch64::B9;
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case AArch64::D10: return AArch64::B10;
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case AArch64::D11: return AArch64::B11;
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case AArch64::D12: return AArch64::B12;
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case AArch64::D13: return AArch64::B13;
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case AArch64::D14: return AArch64::B14;
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case AArch64::D15: return AArch64::B15;
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case AArch64::D16: return AArch64::B16;
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case AArch64::D17: return AArch64::B17;
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case AArch64::D18: return AArch64::B18;
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case AArch64::D19: return AArch64::B19;
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case AArch64::D20: return AArch64::B20;
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case AArch64::D21: return AArch64::B21;
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case AArch64::D22: return AArch64::B22;
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case AArch64::D23: return AArch64::B23;
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case AArch64::D24: return AArch64::B24;
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case AArch64::D25: return AArch64::B25;
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case AArch64::D26: return AArch64::B26;
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case AArch64::D27: return AArch64::B27;
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case AArch64::D28: return AArch64::B28;
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case AArch64::D29: return AArch64::B29;
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case AArch64::D30: return AArch64::B30;
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case AArch64::D31: return AArch64::B31;
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}
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// For anything else, return it unchanged.
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return Reg;
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}
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static inline unsigned getDRegFromBReg(unsigned Reg) {
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switch (Reg) {
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case AArch64::B0: return AArch64::D0;
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case AArch64::B1: return AArch64::D1;
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case AArch64::B2: return AArch64::D2;
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case AArch64::B3: return AArch64::D3;
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case AArch64::B4: return AArch64::D4;
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case AArch64::B5: return AArch64::D5;
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case AArch64::B6: return AArch64::D6;
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case AArch64::B7: return AArch64::D7;
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case AArch64::B8: return AArch64::D8;
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case AArch64::B9: return AArch64::D9;
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case AArch64::B10: return AArch64::D10;
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case AArch64::B11: return AArch64::D11;
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case AArch64::B12: return AArch64::D12;
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case AArch64::B13: return AArch64::D13;
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case AArch64::B14: return AArch64::D14;
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case AArch64::B15: return AArch64::D15;
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case AArch64::B16: return AArch64::D16;
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case AArch64::B17: return AArch64::D17;
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case AArch64::B18: return AArch64::D18;
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case AArch64::B19: return AArch64::D19;
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case AArch64::B20: return AArch64::D20;
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case AArch64::B21: return AArch64::D21;
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case AArch64::B22: return AArch64::D22;
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case AArch64::B23: return AArch64::D23;
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case AArch64::B24: return AArch64::D24;
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case AArch64::B25: return AArch64::D25;
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case AArch64::B26: return AArch64::D26;
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case AArch64::B27: return AArch64::D27;
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case AArch64::B28: return AArch64::D28;
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case AArch64::B29: return AArch64::D29;
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case AArch64::B30: return AArch64::D30;
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case AArch64::B31: return AArch64::D31;
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}
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// For anything else, return it unchanged.
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return Reg;
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}
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namespace AArch64CC {
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// The CondCodes constants map directly to the 4-bit encoding of the condition
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// field for predicated instructions.
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enum CondCode { // Meaning (integer) Meaning (floating-point)
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EQ = 0x0, // Equal Equal
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NE = 0x1, // Not equal Not equal, or unordered
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HS = 0x2, // Unsigned higher or same >, ==, or unordered
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LO = 0x3, // Unsigned lower Less than
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MI = 0x4, // Minus, negative Less than
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PL = 0x5, // Plus, positive or zero >, ==, or unordered
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VS = 0x6, // Overflow Unordered
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VC = 0x7, // No overflow Not unordered
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HI = 0x8, // Unsigned higher Greater than, or unordered
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LS = 0x9, // Unsigned lower or same Less than or equal
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GE = 0xa, // Greater than or equal Greater than or equal
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LT = 0xb, // Less than Less than, or unordered
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GT = 0xc, // Greater than Greater than
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LE = 0xd, // Less than or equal <, ==, or unordered
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AL = 0xe, // Always (unconditional) Always (unconditional)
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NV = 0xf, // Always (unconditional) Always (unconditional)
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// Note the NV exists purely to disassemble 0b1111. Execution is "always".
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Invalid
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};
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inline static const char *getCondCodeName(CondCode Code) {
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switch (Code) {
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default: llvm_unreachable("Unknown condition code");
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case EQ: return "eq";
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case NE: return "ne";
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case HS: return "hs";
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case LO: return "lo";
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case MI: return "mi";
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case PL: return "pl";
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case VS: return "vs";
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case VC: return "vc";
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case HI: return "hi";
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case LS: return "ls";
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case GE: return "ge";
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case LT: return "lt";
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case GT: return "gt";
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case LE: return "le";
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case AL: return "al";
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case NV: return "nv";
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}
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}
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inline static CondCode getInvertedCondCode(CondCode Code) {
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// To reverse a condition it's necessary to only invert the low bit:
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return static_cast<CondCode>(static_cast<unsigned>(Code) ^ 0x1);
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}
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/// Given a condition code, return NZCV flags that would satisfy that condition.
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/// The flag bits are in the format expected by the ccmp instructions.
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/// Note that many different flag settings can satisfy a given condition code,
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/// this function just returns one of them.
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inline static unsigned getNZCVToSatisfyCondCode(CondCode Code) {
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// NZCV flags encoded as expected by ccmp instructions, ARMv8 ISA 5.5.7.
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enum { N = 8, Z = 4, C = 2, V = 1 };
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switch (Code) {
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default: llvm_unreachable("Unknown condition code");
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case EQ: return Z; // Z == 1
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case NE: return 0; // Z == 0
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case HS: return C; // C == 1
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case LO: return 0; // C == 0
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case MI: return N; // N == 1
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case PL: return 0; // N == 0
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case VS: return V; // V == 1
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case VC: return 0; // V == 0
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case HI: return C; // C == 1 && Z == 0
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case LS: return 0; // C == 0 || Z == 1
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case GE: return 0; // N == V
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case LT: return N; // N != V
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case GT: return 0; // Z == 0 && N == V
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case LE: return Z; // Z == 1 || N != V
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}
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}
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} // end namespace AArch64CC
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struct SysAlias {
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const char *Name;
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uint16_t Encoding;
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FeatureBitset FeaturesRequired;
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SysAlias (const char *N, uint16_t E) : Name(N), Encoding(E) {};
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SysAlias (const char *N, uint16_t E, FeatureBitset F) :
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Name(N), Encoding(E), FeaturesRequired(F) {};
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bool haveFeatures(FeatureBitset ActiveFeatures) const {
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return (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
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}
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FeatureBitset getRequiredFeatures() const { return FeaturesRequired; }
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};
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struct SysAliasReg : SysAlias {
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bool NeedsReg;
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SysAliasReg(const char *N, uint16_t E, bool R) : SysAlias(N, E), NeedsReg(R) {};
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};
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namespace AArch64AT{
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struct AT : SysAlias {
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using SysAlias::SysAlias;
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};
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#define GET_AT_DECL
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#include "AArch64GenSystemOperands.inc"
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}
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namespace AArch64DB {
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struct DB : SysAlias {
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using SysAlias::SysAlias;
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};
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#define GET_DB_DECL
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#include "AArch64GenSystemOperands.inc"
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}
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namespace AArch64DC {
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struct DC : SysAlias {
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using SysAlias::SysAlias;
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};
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#define GET_DC_DECL
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#include "AArch64GenSystemOperands.inc"
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}
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namespace AArch64IC {
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struct IC : SysAliasReg {
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using SysAliasReg::SysAliasReg;
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};
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#define GET_IC_DECL
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#include "AArch64GenSystemOperands.inc"
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}
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namespace AArch64ISB {
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struct ISB : SysAlias {
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using SysAlias::SysAlias;
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};
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#define GET_ISB_DECL
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#include "AArch64GenSystemOperands.inc"
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}
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namespace AArch64PRFM {
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struct PRFM : SysAlias {
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using SysAlias::SysAlias;
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};
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#define GET_PRFM_DECL
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#include "AArch64GenSystemOperands.inc"
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}
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namespace AArch64PState {
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struct PState : SysAlias{
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using SysAlias::SysAlias;
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};
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#define GET_PSTATE_DECL
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#include "AArch64GenSystemOperands.inc"
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}
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namespace AArch64PSBHint {
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struct PSB : SysAlias {
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using SysAlias::SysAlias;
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};
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#define GET_PSB_DECL
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#include "AArch64GenSystemOperands.inc"
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}
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namespace AArch64SE {
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enum ShiftExtSpecifiers {
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Invalid = -1,
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LSL,
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MSL,
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LSR,
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ASR,
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ROR,
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UXTB,
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UXTH,
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UXTW,
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UXTX,
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SXTB,
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SXTH,
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SXTW,
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SXTX
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};
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}
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namespace AArch64Layout {
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enum VectorLayout {
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Invalid = -1,
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VL_8B,
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VL_4H,
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VL_2S,
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VL_1D,
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VL_16B,
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VL_8H,
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VL_4S,
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VL_2D,
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// Bare layout for the 128-bit vector
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// (only show ".b", ".h", ".s", ".d" without vector number)
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VL_B,
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VL_H,
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VL_S,
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VL_D
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};
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}
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inline static const char *
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AArch64VectorLayoutToString(AArch64Layout::VectorLayout Layout) {
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switch (Layout) {
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case AArch64Layout::VL_8B: return ".8b";
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case AArch64Layout::VL_4H: return ".4h";
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case AArch64Layout::VL_2S: return ".2s";
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case AArch64Layout::VL_1D: return ".1d";
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case AArch64Layout::VL_16B: return ".16b";
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case AArch64Layout::VL_8H: return ".8h";
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case AArch64Layout::VL_4S: return ".4s";
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case AArch64Layout::VL_2D: return ".2d";
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case AArch64Layout::VL_B: return ".b";
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case AArch64Layout::VL_H: return ".h";
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case AArch64Layout::VL_S: return ".s";
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case AArch64Layout::VL_D: return ".d";
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default: llvm_unreachable("Unknown Vector Layout");
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}
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}
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inline static AArch64Layout::VectorLayout
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AArch64StringToVectorLayout(StringRef LayoutStr) {
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return StringSwitch<AArch64Layout::VectorLayout>(LayoutStr)
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.Case(".8b", AArch64Layout::VL_8B)
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.Case(".4h", AArch64Layout::VL_4H)
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.Case(".2s", AArch64Layout::VL_2S)
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.Case(".1d", AArch64Layout::VL_1D)
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.Case(".16b", AArch64Layout::VL_16B)
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.Case(".8h", AArch64Layout::VL_8H)
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.Case(".4s", AArch64Layout::VL_4S)
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.Case(".2d", AArch64Layout::VL_2D)
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.Case(".b", AArch64Layout::VL_B)
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.Case(".h", AArch64Layout::VL_H)
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.Case(".s", AArch64Layout::VL_S)
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.Case(".d", AArch64Layout::VL_D)
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.Default(AArch64Layout::Invalid);
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}
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namespace AArch64SysReg {
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struct SysReg {
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const char *Name;
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unsigned Encoding;
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bool Readable;
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bool Writeable;
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FeatureBitset FeaturesRequired;
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bool haveFeatures(FeatureBitset ActiveFeatures) const {
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return (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
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}
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};
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#define GET_SYSREG_DECL
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#include "AArch64GenSystemOperands.inc"
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const SysReg *lookupSysRegByName(StringRef);
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const SysReg *lookupSysRegByEncoding(uint16_t);
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uint32_t parseGenericRegister(StringRef Name);
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std::string genericRegisterString(uint32_t Bits);
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}
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namespace AArch64TLBI {
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struct TLBI : SysAliasReg {
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using SysAliasReg::SysAliasReg;
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};
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#define GET_TLBI_DECL
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#include "AArch64GenSystemOperands.inc"
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}
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namespace AArch64II {
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/// Target Operand Flag enum.
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enum TOF {
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//===------------------------------------------------------------------===//
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// AArch64 Specific MachineOperand flags.
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MO_NO_FLAG,
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MO_FRAGMENT = 0xf,
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/// MO_PAGE - A symbol operand with this flag represents the pc-relative
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/// offset of the 4K page containing the symbol. This is used with the
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/// ADRP instruction.
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MO_PAGE = 1,
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/// MO_PAGEOFF - A symbol operand with this flag represents the offset of
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/// that symbol within a 4K page. This offset is added to the page address
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/// to produce the complete address.
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MO_PAGEOFF = 2,
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/// MO_G3 - A symbol operand with this flag (granule 3) represents the high
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/// 16-bits of a 64-bit address, used in a MOVZ or MOVK instruction
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MO_G3 = 3,
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/// MO_G2 - A symbol operand with this flag (granule 2) represents the bits
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/// 32-47 of a 64-bit address, used in a MOVZ or MOVK instruction
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MO_G2 = 4,
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/// MO_G1 - A symbol operand with this flag (granule 1) represents the bits
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/// 16-31 of a 64-bit address, used in a MOVZ or MOVK instruction
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MO_G1 = 5,
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/// MO_G0 - A symbol operand with this flag (granule 0) represents the bits
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/// 0-15 of a 64-bit address, used in a MOVZ or MOVK instruction
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MO_G0 = 6,
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/// MO_HI12 - This flag indicates that a symbol operand represents the bits
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/// 13-24 of a 64-bit address, used in a arithmetic immediate-shifted-left-
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/// by-12-bits instruction.
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MO_HI12 = 7,
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/// MO_GOT - This flag indicates that a symbol operand represents the
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/// address of the GOT entry for the symbol, rather than the address of
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/// the symbol itself.
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MO_GOT = 0x10,
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/// MO_NC - Indicates whether the linker is expected to check the symbol
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/// reference for overflow. For example in an ADRP/ADD pair of relocations
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/// the ADRP usually does check, but not the ADD.
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MO_NC = 0x20,
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/// MO_TLS - Indicates that the operand being accessed is some kind of
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/// thread-local symbol. On Darwin, only one type of thread-local access
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/// exists (pre linker-relaxation), but on ELF the TLSModel used for the
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/// referee will affect interpretation.
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MO_TLS = 0x40
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};
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} // end namespace AArch64II
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} // end namespace llvm
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#endif
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