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136 lines
3.7 KiB
C++
136 lines
3.7 KiB
C++
//===- ARMInstrInfo.cpp - ARM Instruction Information -----------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the ARM implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "ARMInstrInfo.h"
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#include "ARM.h"
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#include "ARMAddressingModes.h"
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#include "ARMGenInstrInfo.inc"
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#include "ARMMachineFunctionInfo.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/CodeGen/LiveVariables.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineJumpTableInfo.h"
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#include "llvm/Target/TargetAsmInfo.h"
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#include "llvm/Support/CommandLine.h"
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using namespace llvm;
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ARMInstrInfo::ARMInstrInfo(const ARMSubtarget &STI)
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: ARMBaseInstrInfo(STI), RI(*this, STI) {
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}
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unsigned ARMInstrInfo::
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getUnindexedOpcode(unsigned Opc) const {
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switch (Opc) {
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default: break;
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case ARM::LDR_PRE:
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case ARM::LDR_POST:
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return ARM::LDR;
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case ARM::LDRH_PRE:
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case ARM::LDRH_POST:
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return ARM::LDRH;
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case ARM::LDRB_PRE:
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case ARM::LDRB_POST:
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return ARM::LDRB;
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case ARM::LDRSH_PRE:
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case ARM::LDRSH_POST:
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return ARM::LDRSH;
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case ARM::LDRSB_PRE:
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case ARM::LDRSB_POST:
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return ARM::LDRSB;
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case ARM::STR_PRE:
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case ARM::STR_POST:
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return ARM::STR;
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case ARM::STRH_PRE:
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case ARM::STRH_POST:
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return ARM::STRH;
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case ARM::STRB_PRE:
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case ARM::STRB_POST:
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return ARM::STRB;
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}
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return 0;
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}
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unsigned ARMInstrInfo::
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getOpcode(ARMII::Op Op) const {
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switch (Op) {
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case ARMII::ADDri: return ARM::ADDri;
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case ARMII::ADDrs: return ARM::ADDrs;
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case ARMII::ADDrr: return ARM::ADDrr;
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case ARMII::B: return ARM::B;
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case ARMII::Bcc: return ARM::Bcc;
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case ARMII::BR_JTr: return ARM::BR_JTr;
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case ARMII::BR_JTm: return ARM::BR_JTm;
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case ARMII::BR_JTadd: return ARM::BR_JTadd;
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case ARMII::BX_RET: return ARM::BX_RET;
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case ARMII::FCPYS: return ARM::FCPYS;
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case ARMII::FCPYD: return ARM::FCPYD;
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case ARMII::FLDD: return ARM::FLDD;
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case ARMII::FLDS: return ARM::FLDS;
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case ARMII::FSTD: return ARM::FSTD;
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case ARMII::FSTS: return ARM::FSTS;
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case ARMII::LDR: return ARM::LDR;
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case ARMII::MOVr: return ARM::MOVr;
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case ARMII::STR: return ARM::STR;
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case ARMII::SUBri: return ARM::SUBri;
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case ARMII::SUBrs: return ARM::SUBrs;
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case ARMII::SUBrr: return ARM::SUBrr;
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case ARMII::VMOVD: return ARM::VMOVD;
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case ARMII::VMOVQ: return ARM::VMOVQ;
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default:
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break;
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}
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return 0;
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}
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bool ARMInstrInfo::
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BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
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if (MBB.empty()) return false;
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switch (MBB.back().getOpcode()) {
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case ARM::BX_RET: // Return.
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case ARM::LDM_RET:
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case ARM::B:
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case ARM::BR_JTr: // Jumptable branch.
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case ARM::BR_JTm: // Jumptable branch through mem.
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case ARM::BR_JTadd: // Jumptable branch add to pc.
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return true;
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default:
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break;
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}
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return false;
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}
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void ARMInstrInfo::
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reMaterialize(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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unsigned DestReg,
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const MachineInstr *Orig) const {
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DebugLoc dl = Orig->getDebugLoc();
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if (Orig->getOpcode() == ARM::MOVi2pieces) {
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RI.emitLoadConstPool(MBB, I, dl,
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DestReg,
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Orig->getOperand(1).getImm(),
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(ARMCC::CondCodes)Orig->getOperand(2).getImm(),
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Orig->getOperand(3).getReg());
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return;
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}
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MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
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MI->getOperand(0).setReg(DestReg);
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MBB.insert(I, MI);
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}
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