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6aff2cf35d
If pseudoToMCOpcode failed, we would return the original opcode, so operands would be swapped, but the instruction would remain the same. It resulted in LSHLREV a, b ---> LSHLREV b, a. This fixes Glamor text rendering and piglit/arb_sample_shading-builtin-gl-sample-mask on VI. This is a candidate for stable branches. v2: the test was simplified by Tom Stellard llvm-svn: 240824
34 lines
1.3 KiB
LLVM
34 lines
1.3 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
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; GCN-LABEL: {{^}}main:
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; SI: v_lshl_b32_e32 v{{[0-9]+}}, 1, v{{[0-9]+}}
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; VI: v_lshlrev_b32_e64 v{{[0-9]+}}, v{{[0-9]+}}, 1
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define void @main() #0 {
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main_body:
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%0 = fptosi float undef to i32
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%1 = call <4 x i32> @llvm.SI.imageload.v4i32(<4 x i32> undef, <32 x i8> undef, i32 2)
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%2 = extractelement <4 x i32> %1, i32 0
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%3 = and i32 %0, 7
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%4 = shl i32 1, %3
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%5 = and i32 %2, %4
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%6 = icmp eq i32 %5, 0
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%.10 = select i1 %6, float 0.000000e+00, float undef
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%7 = call i32 @llvm.SI.packf16(float undef, float %.10)
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%8 = bitcast i32 %7 to float
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call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float undef, float %8, float undef, float %8)
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ret void
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}
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; Function Attrs: nounwind readnone
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declare <4 x i32> @llvm.SI.imageload.v4i32(<4 x i32>, <32 x i8>, i32) #1
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; Function Attrs: nounwind readnone
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declare i32 @llvm.SI.packf16(float, float) #1
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declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
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attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" }
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attributes #1 = { nounwind readnone }
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