Kit Barton 8b3a860234 [Power9] Implement new vsx instructions: load, store instructions for vector and scalar ...

We follow the comments mentioned in http://reviews.llvm.org/D16842#344378 to
implement this new patch.

This patch implements the following vsx instructions:

Vector load/store:
lxv lxvx lxvb16x lxvl lxvll lxvh8x lxvwsx
stxv stxvb16x stxvh8x stxvl stxvll stxvx
Scalar load/store:
lxsd lxssp lxsibzx lxsihzx
stxsd stxssp stxsibx stxsihx
21 instructions

Phabricator: http://reviews.llvm.org/D16919
llvm-svn: 262906

2016-03-08 03:49:13 +00:00

..

AArch64

AArch64: remove CRC feature from Cyclone.

2016-02-24 18:10:17 +00:00

AMDGPU

AMDGPU/SI: add llvm.amdgcn.image.atomic.* intrinsics

2016-03-04 10:39:50 +00:00

ARM

ARM: disallow pc as a base register in Thumb2 memory ops.

2016-02-25 16:54:52 +00:00

AsmParser

AsmParser: Fix nested .irp/.irpc

2016-03-01 08:18:28 +00:00

COFF

[codeview] Dump def range lengths in hex

2016-02-11 23:40:14 +00:00

Disassembler

[Power9] Implement new vsx instructions: load, store instructions for vector and scalar

2016-03-08 03:49:13 +00:00

ELF

Accept subtractions involving a weak symbol.

2016-01-20 18:57:48 +00:00

Hexagon

[Hexagon] As a size optimization, not lazy extending TPREL or DTPREL variants since they're usually in range.

2016-02-29 21:21:56 +00:00

MachO

Form reform for MCDwarf.

2015-12-23 01:57:31 +00:00

Markup

…

Mips

[mips] Range check uimm20 and fixed a bug this revealed.

2016-02-29 16:06:38 +00:00

PowerPC

[Power9] Implement new vsx instructions: load, store instructions for vector and scalar

2016-03-08 03:49:13 +00:00

Sparc

Addition of tests to previous check-in. Tests for coprocessor register usage in Sparc.

2016-02-27 12:52:26 +00:00

SystemZ

[SystemZ] Sort relocs to avoid code corruption by linker optimization

2015-12-16 18:12:40 +00:00

X86

[X86] Make X86MCCodeEmitter::DetermineREXPrefix locate operands more like how VEX prefix handling does.

2016-03-02 07:32:43 +00:00