.. |
AArch64
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[ARM, AArch64] Match additional patterns to ldN instructions
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2016-05-19 21:39:00 +00:00 |
AMDGPU
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AMDGPU: Fix promote alloca for pointer loads
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2016-05-18 23:20:24 +00:00 |
ARM
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[ARM, AArch64] Match additional patterns to ldN instructions
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2016-05-19 21:39:00 +00:00 |
BPF
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[llc] New diagnostic handler
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2016-05-16 14:28:02 +00:00 |
Generic
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llc: Rework -run-pass option
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2016-05-10 01:32:44 +00:00 |
Hexagon
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When looking for a spill slot in reg scavenger, find one that matches RC
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2016-05-18 18:16:00 +00:00 |
Inputs
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[PR27284] Reverse the ownership between DICompileUnit and DISubprogram.
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2016-04-15 15:57:41 +00:00 |
Lanai
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[lanai] Add subword scheduling itineraries.
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2016-04-20 18:28:55 +00:00 |
Mips
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[mips][mips16] Fix ZERO is not a CPU16Regs register error from the machine verifier.
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2016-05-19 10:42:14 +00:00 |
MIR
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[llc] New diagnostic handler
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2016-05-16 14:28:02 +00:00 |
MSP430
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NVPTX
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[NVPTX] Fix sign/zero-extending ldg/ldu instruction selection
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2016-05-02 18:12:02 +00:00 |
PowerPC
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Simplify handling of hidden stubs on PowerPC.
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2016-05-20 12:00:52 +00:00 |
SPARC
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[Sparc] Enable more inline assembly constraints.
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2016-05-20 09:03:01 +00:00 |
SystemZ
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[SystemZ] Fix register ordering for BinaryRRF instructions
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2016-05-18 13:24:57 +00:00 |
Thumb
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ARM: stop emitting blx instructions for most calls on MachO.
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2016-05-10 19:17:47 +00:00 |
Thumb2
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ARM: stop emitting blx instructions for most calls on MachO.
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2016-05-10 19:17:47 +00:00 |
WebAssembly
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[WebAssembly] Make several CHECK lines less fragile using regexes and CHECK-DAG.
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2016-05-19 01:52:56 +00:00 |
WinEH
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[PR27284] Reverse the ownership between DICompileUnit and DISubprogram.
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2016-04-15 15:57:41 +00:00 |
X86
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[X86] Run the AVX/AVX2 intrinsic tests in AVX512VL mode too just to make sure we don't break any older intrinsics.
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2016-05-20 05:10:32 +00:00 |
XCore
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[PR27284] Reverse the ownership between DICompileUnit and DISubprogram.
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2016-04-15 15:57:41 +00:00 |