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f58aee7cea
Summary: Also explicitly port over some tests in llvm.amdgcn.image.* that were missing. Some tests are removed because they no longer apply (i.e. explicitly testing building an address vector via insertelement). This is in preparation for the eventual removal of the old-style intrinsics. Some additional notes: - constant-address-space-32bit.ll: change some GCN-NEXT to GCN because the instruction schedule was subtly altered - insert_vector_elt.ll: the old test didn't actually test anything, because %tmp1 was not used; remove the load, because it doesn't work (Because of the amdgpu_ps calling convention? In any case, it's orthogonal to what the test claims to be testing.) Change-Id: Idfa99b6512ad139e755e82b8b89548ab08f0afcf Reviewers: arsenm, rampitec Subscribers: MatzeB, qcolombet, kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D48018 llvm-svn: 335229
29 lines
1.2 KiB
LLVM
29 lines
1.2 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
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; GCN-LABEL: {{^}}main:
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; SI: v_lshl_b32_e32 v{{[0-9]+}}, 1, v{{[0-9]+}}
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; VI: v_lshlrev_b32_e64 v{{[0-9]+}}, v{{[0-9]+}}, 1
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define amdgpu_ps float @main(float %arg0, float %arg1) #0 {
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bb:
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%tmp = fptosi float %arg0 to i32
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%tmp1 = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32(i32 15, i32 undef, <8 x i32> undef, i32 0, i32 0)
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%tmp2.f = extractelement <4 x float> %tmp1, i32 0
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%tmp2 = bitcast float %tmp2.f to i32
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%tmp3 = and i32 %tmp, 7
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%tmp4 = shl i32 1, %tmp3
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%tmp5 = and i32 %tmp2, %tmp4
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%tmp6 = icmp eq i32 %tmp5, 0
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%tmp7 = select i1 %tmp6, float 0.000000e+00, float %arg1
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%tmp8 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float undef, float %tmp7)
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%tmp9 = bitcast <2 x half> %tmp8 to float
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ret float %tmp9
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}
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declare <2 x half> @llvm.amdgcn.cvt.pkrtz(float, float) #1
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declare <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32(i32, i32, <8 x i32>, i32, i32) #2
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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attributes #2 = { nounwind readonly }
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