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https://github.com/RPCS3/llvm-mirror.git
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11308327e5
Summary: This change is the first part of the AMDGPU target description change. The aim of it is the effective splitting the vector and scalar flows at the selection stage. Selection uses predicate functions based on the framework implemented earlier - https://reviews.llvm.org/D35267 Differential revision: https://reviews.llvm.org/D52019 Reviewers: rampitec llvm-svn: 342719
204 lines
8.5 KiB
LLVM
204 lines
8.5 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN -check-prefix=FUNC %s
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declare i32 @llvm.r600.read.tidig.x() nounwind readnone
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declare i64 @llvm.ctpop.i64(i64) nounwind readnone
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declare <2 x i64> @llvm.ctpop.v2i64(<2 x i64>) nounwind readnone
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declare <4 x i64> @llvm.ctpop.v4i64(<4 x i64>) nounwind readnone
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declare <8 x i64> @llvm.ctpop.v8i64(<8 x i64>) nounwind readnone
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declare <16 x i64> @llvm.ctpop.v16i64(<16 x i64>) nounwind readnone
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declare i65 @llvm.ctpop.i65(i65) nounwind readnone
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declare i128 @llvm.ctpop.i128(i128) nounwind readnone
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; FUNC-LABEL: {{^}}s_ctpop_i64:
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; SI: s_load_dwordx2 [[SVAL:s\[[0-9]+:[0-9]+\]]], s{{\[[0-9]+:[0-9]+\]}}, 0x13
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; VI: s_load_dwordx2 [[SVAL:s\[[0-9]+:[0-9]+\]]], s{{\[[0-9]+:[0-9]+\]}}, 0x4c
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; GCN: s_bcnt1_i32_b64 [[SRESULT:s[0-9]+]], [[SVAL]]
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; GCN: v_mov_b32_e32 [[VRESULT:v[0-9]+]], [[SRESULT]]
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; GCN: buffer_store_dword [[VRESULT]],
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; GCN: s_endpgm
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define amdgpu_kernel void @s_ctpop_i64(i32 addrspace(1)* noalias %out, [8 x i32], i64 %val) nounwind {
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%ctpop = call i64 @llvm.ctpop.i64(i64 %val) nounwind readnone
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%truncctpop = trunc i64 %ctpop to i32
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store i32 %truncctpop, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}v_ctpop_i64:
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; GCN: {{buffer|flat}}_load_dwordx2 v{{\[}}[[LOVAL:[0-9]+]]:[[HIVAL:[0-9]+]]{{\]}},
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; GCN: v_bcnt_u32_b32{{(_e64)*}} [[MIDRESULT:v[0-9]+]], v[[LOVAL]], 0
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; SI-NEXT: v_bcnt_u32_b32_e32 [[RESULT:v[0-9]+]], v[[HIVAL]], [[MIDRESULT]]
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; VI-NEXT: v_bcnt_u32_b32 [[RESULT:v[0-9]+]], v[[HIVAL]], [[MIDRESULT]]
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; GCN: buffer_store_dword [[RESULT]],
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; GCN: s_endpgm
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define amdgpu_kernel void @v_ctpop_i64(i32 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in) nounwind {
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%tid = call i32 @llvm.r600.read.tidig.x()
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%in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %tid
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%val = load i64, i64 addrspace(1)* %in.gep, align 8
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%ctpop = call i64 @llvm.ctpop.i64(i64 %val) nounwind readnone
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%truncctpop = trunc i64 %ctpop to i32
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store i32 %truncctpop, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}v_ctpop_i64_user:
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; GCN: {{buffer|flat}}_load_dwordx2 v{{\[}}[[LOVAL:[0-9]+]]:[[HIVAL:[0-9]+]]{{\]}},
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; GCN: v_bcnt_u32_b32{{(_e64)*}} [[MIDRESULT:v[0-9]+]], v[[LOVAL]], 0
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; SI-NEXT: v_bcnt_u32_b32_e32 [[RESULT:v[0-9]+]], v[[HIVAL]], [[MIDRESULT]]
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; VI-NEXT: v_bcnt_u32_b32 [[RESULT:v[0-9]+]], v[[HIVAL]], [[MIDRESULT]]
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; GCN-DAG: v_or_b32_e32 v[[RESULT_LO:[0-9]+]], s{{[0-9]+}}, [[RESULT]]
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; GCN-DAG: v_mov_b32_e32 v[[RESULT_HI:[0-9]+]], s{{[0-9]+}}
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; GCN: buffer_store_dwordx2 v{{\[}}[[RESULT_LO]]:[[RESULT_HI]]{{\]}}
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; GCN: s_endpgm
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define amdgpu_kernel void @v_ctpop_i64_user(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in, i64 %s.val) nounwind {
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%tid = call i32 @llvm.r600.read.tidig.x()
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%in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %tid
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%val = load i64, i64 addrspace(1)* %in.gep, align 8
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%ctpop = call i64 @llvm.ctpop.i64(i64 %val) nounwind readnone
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%or = or i64 %ctpop, %s.val
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store i64 %or, i64 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}s_ctpop_v2i64:
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; GCN: s_bcnt1_i32_b64
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; GCN: s_bcnt1_i32_b64
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; GCN: s_endpgm
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define amdgpu_kernel void @s_ctpop_v2i64(<2 x i32> addrspace(1)* noalias %out, <2 x i64> %val) nounwind {
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%ctpop = call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %val) nounwind readnone
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%truncctpop = trunc <2 x i64> %ctpop to <2 x i32>
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store <2 x i32> %truncctpop, <2 x i32> addrspace(1)* %out, align 8
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ret void
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}
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; FUNC-LABEL: {{^}}s_ctpop_v4i64:
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; GCN: s_bcnt1_i32_b64
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; GCN: s_bcnt1_i32_b64
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; GCN: s_bcnt1_i32_b64
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; GCN: s_bcnt1_i32_b64
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; GCN: s_endpgm
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define amdgpu_kernel void @s_ctpop_v4i64(<4 x i32> addrspace(1)* noalias %out, <4 x i64> %val) nounwind {
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%ctpop = call <4 x i64> @llvm.ctpop.v4i64(<4 x i64> %val) nounwind readnone
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%truncctpop = trunc <4 x i64> %ctpop to <4 x i32>
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store <4 x i32> %truncctpop, <4 x i32> addrspace(1)* %out, align 16
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ret void
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}
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; FUNC-LABEL: {{^}}v_ctpop_v2i64:
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; GCN: v_bcnt_u32_b32
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; GCN: v_bcnt_u32_b32
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; GCN: v_bcnt_u32_b32
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; GCN: v_bcnt_u32_b32
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; GCN: s_endpgm
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define amdgpu_kernel void @v_ctpop_v2i64(<2 x i32> addrspace(1)* noalias %out, <2 x i64> addrspace(1)* noalias %in) nounwind {
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%tid = call i32 @llvm.r600.read.tidig.x()
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%in.gep = getelementptr <2 x i64>, <2 x i64> addrspace(1)* %in, i32 %tid
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%val = load <2 x i64>, <2 x i64> addrspace(1)* %in.gep, align 16
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%ctpop = call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %val) nounwind readnone
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%truncctpop = trunc <2 x i64> %ctpop to <2 x i32>
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store <2 x i32> %truncctpop, <2 x i32> addrspace(1)* %out, align 8
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ret void
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}
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; FUNC-LABEL: {{^}}v_ctpop_v4i64:
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; GCN: v_bcnt_u32_b32
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; GCN: v_bcnt_u32_b32
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; GCN: v_bcnt_u32_b32
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; GCN: v_bcnt_u32_b32
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; GCN: v_bcnt_u32_b32
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; GCN: v_bcnt_u32_b32
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; GCN: v_bcnt_u32_b32
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; GCN: v_bcnt_u32_b32
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; GCN: s_endpgm
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define amdgpu_kernel void @v_ctpop_v4i64(<4 x i32> addrspace(1)* noalias %out, <4 x i64> addrspace(1)* noalias %in) nounwind {
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%tid = call i32 @llvm.r600.read.tidig.x()
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%in.gep = getelementptr <4 x i64>, <4 x i64> addrspace(1)* %in, i32 %tid
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%val = load <4 x i64>, <4 x i64> addrspace(1)* %in.gep, align 32
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%ctpop = call <4 x i64> @llvm.ctpop.v4i64(<4 x i64> %val) nounwind readnone
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%truncctpop = trunc <4 x i64> %ctpop to <4 x i32>
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store <4 x i32> %truncctpop, <4 x i32> addrspace(1)* %out, align 16
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ret void
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}
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; FUNC-LABEL: {{^}}ctpop_i64_in_br:
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; SI-DAG: s_load_dwordx2 s{{\[}}[[LOVAL:[0-9]+]]:[[HIVAL:[0-9]+]]{{\]}}, s[{{[0-9]+:[0-9]+}}], 0xd
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; VI-DAG: s_load_dwordx2 s{{\[}}[[LOVAL:[0-9]+]]:[[HIVAL:[0-9]+]]{{\]}}, s[{{[0-9]+:[0-9]+}}], 0x34
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; GCN-DAG: s_bcnt1_i32_b64 [[RESULT:s[0-9]+]], {{s\[}}[[LOVAL]]:[[HIVAL]]{{\]}}
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; GCN-DAG: s_mov_b32 [[ZERO:s[0-9]+]], 0
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; GCN-DAG: v_mov_b32_e32 v[[VLO:[0-9]+]], [[RESULT]]
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; GCN-DAG: v_mov_b32_e32 v[[VHI:[0-9]+]], [[ZERO]]
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; GCN: buffer_store_dwordx2 {{v\[}}[[VLO]]:[[VHI]]{{\]}}
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; GCN: s_endpgm
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define amdgpu_kernel void @ctpop_i64_in_br(i64 addrspace(1)* %out, i64 addrspace(1)* %in, i64 %ctpop_arg, i32 %cond) {
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entry:
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%tmp0 = icmp eq i32 %cond, 0
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br i1 %tmp0, label %if, label %else
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if:
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%tmp2 = call i64 @llvm.ctpop.i64(i64 %ctpop_arg)
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br label %endif
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else:
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%tmp3 = getelementptr i64, i64 addrspace(1)* %in, i32 1
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%tmp4 = load i64, i64 addrspace(1)* %tmp3
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br label %endif
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endif:
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%tmp5 = phi i64 [%tmp2, %if], [%tmp4, %else]
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store i64 %tmp5, i64 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}s_ctpop_i128:
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; GCN: s_bcnt1_i32_b64 [[SRESULT0:s[0-9]+]],
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; GCN: s_bcnt1_i32_b64 [[SRESULT1:s[0-9]+]],
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; GCN: s_add_i32 s{{[0-9]+}}, [[SRESULT1]], [[SRESULT0]]
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; GCN: s_endpgm
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define amdgpu_kernel void @s_ctpop_i128(i32 addrspace(1)* noalias %out, i128 %val) nounwind {
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%ctpop = call i128 @llvm.ctpop.i128(i128 %val) nounwind readnone
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%truncctpop = trunc i128 %ctpop to i32
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store i32 %truncctpop, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}s_ctpop_i65:
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; GCN: s_bcnt1_i32_b64 [[REG0:s[0-9]+]],
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; GCN: s_and_b32
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; GCN: s_bcnt1_i32_b64 [[REG1:s[0-9]+]],
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; GCN: s_add_i32 {{s[0-9]+}}, [[REG0]], [[REG1]]
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; GCN: s_endpgm
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define amdgpu_kernel void @s_ctpop_i65(i32 addrspace(1)* noalias %out, i65 %val) nounwind {
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%ctpop = call i65 @llvm.ctpop.i65(i65 %val) nounwind readnone
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%truncctpop = trunc i65 %ctpop to i32
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store i32 %truncctpop, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FIXME: Should not have extra add
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; FUNC-LABEL: {{^}}v_ctpop_i128:
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; SI: buffer_load_dwordx4 v{{\[}}[[VAL0:[0-9]+]]:[[VAL3:[0-9]+]]{{\]}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64
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; VI: flat_load_dwordx4 v{{\[}}[[VAL0:[0-9]+]]:[[VAL3:[0-9]+]]{{\]}}, v{{\[[0-9]+:[0-9]+\]}}
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; GCN-DAG: v_bcnt_u32_b32{{(_e64)*}} [[MIDRESULT0:v[0-9]+]], v{{[0-9]+}}, 0
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; GCN-DAG: v_bcnt_u32_b32{{(_e32)*(_e64)*}} [[MIDRESULT1:v[0-9]+]], v[[VAL3]], [[MIDRESULT0]]
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; GCN-DAG: v_bcnt_u32_b32{{(_e64)*}} [[MIDRESULT2:v[0-9]+]], v[[VAL0]], 0
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; GCN-DAG: v_bcnt_u32_b32{{(_e32)*(_e64)*}} [[MIDRESULT3:v[0-9]+]], v{{[0-9]+}}, [[MIDRESULT2]]
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; GCN: v_add_{{[iu]}}32_e32 [[RESULT:v[0-9]+]], vcc, [[MIDRESULT2]], [[MIDRESULT1]]
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; GCN: buffer_store_dword [[RESULT]],
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; GCN: s_endpgm
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define amdgpu_kernel void @v_ctpop_i128(i32 addrspace(1)* noalias %out, i128 addrspace(1)* noalias %in) nounwind {
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%tid = call i32 @llvm.r600.read.tidig.x()
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%in.gep = getelementptr i128, i128 addrspace(1)* %in, i32 %tid
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%val = load i128, i128 addrspace(1)* %in.gep, align 8
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%ctpop = call i128 @llvm.ctpop.i128(i128 %val) nounwind readnone
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%truncctpop = trunc i128 %ctpop to i32
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store i32 %truncctpop, i32 addrspace(1)* %out, align 4
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ret void
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}
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