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252673a9d9
See https://reviews.llvm.org/D47106 for details. Reviewed By: probinson Differential Revision: https://reviews.llvm.org/D47171 This commit drops that patch's changes to: llvm/test/CodeGen/NVPTX/f16x2-instructions.ll llvm/test/CodeGen/NVPTX/param-load-store.ll For some reason, the dos line endings there prevent me from commiting via the monorepo. A follow-up commit (not via the monorepo) will finish the patch. llvm-svn: 336843
89 lines
3.4 KiB
LLVM
89 lines
3.4 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=SI %s
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declare i32 @llvm.amdgcn.workitem.id.x() #1
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; Test with inline immediate
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; FUNC-LABEL: {{^}}shl_2_add_9_i32:
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; SI: v_lshlrev_b32_e32 [[REG:v[0-9]+]], 2, {{v[0-9]+}}
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; SI: v_add_i32_e32 [[RESULT:v[0-9]+]], vcc, 36, [[REG]]
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; SI: buffer_store_dword [[RESULT]]
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; SI: s_endpgm
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define amdgpu_kernel void @shl_2_add_9_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 {
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%tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1
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%ptr = getelementptr i32, i32 addrspace(1)* %in, i32 %tid.x
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%val = load i32, i32 addrspace(1)* %ptr, align 4
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%add = add i32 %val, 9
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%result = shl i32 %add, 2
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store i32 %result, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}shl_2_add_9_i32_2_add_uses:
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; SI-DAG: v_add_i32_e32 [[ADDREG:v[0-9]+]], vcc, 9, {{v[0-9]+}}
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; SI-DAG: v_lshlrev_b32_e32 [[SHLREG:v[0-9]+]], 2, {{v[0-9]+}}
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; SI-DAG: buffer_store_dword [[ADDREG]]
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; SI-DAG: buffer_store_dword [[SHLREG]]
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; SI: s_endpgm
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define amdgpu_kernel void @shl_2_add_9_i32_2_add_uses(i32 addrspace(1)* %out0, i32 addrspace(1)* %out1, i32 addrspace(1)* %in) #0 {
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%tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1
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%ptr = getelementptr i32, i32 addrspace(1)* %in, i32 %tid.x
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%val = load i32, i32 addrspace(1)* %ptr, align 4
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%add = add i32 %val, 9
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%result = shl i32 %add, 2
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store i32 %result, i32 addrspace(1)* %out0, align 4
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store i32 %add, i32 addrspace(1)* %out1, align 4
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ret void
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}
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; Test with add literal constant
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; FUNC-LABEL: {{^}}shl_2_add_999_i32:
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; SI: v_lshlrev_b32_e32 [[REG:v[0-9]+]], 2, {{v[0-9]+}}
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; SI: v_add_i32_e32 [[RESULT:v[0-9]+]], vcc, 0xf9c, [[REG]]
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; SI: buffer_store_dword [[RESULT]]
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; SI: s_endpgm
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define amdgpu_kernel void @shl_2_add_999_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 {
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%tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1
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%ptr = getelementptr i32, i32 addrspace(1)* %in, i32 %tid.x
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%val = load i32, i32 addrspace(1)* %ptr, align 4
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%shl = add i32 %val, 999
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%result = shl i32 %shl, 2
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store i32 %result, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}test_add_shl_add_constant:
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; SI-DAG: s_load_dwordx2 s{{\[}}[[X:[0-9]+]]:[[Y:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x13
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; SI-DAG: s_lshl_b32 [[SHL3:s[0-9]+]], s[[X]], 3
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; SI: s_add_i32 [[RESULT:s[0-9]+]], [[SHL3]], s[[Y]]
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; SI: s_addk_i32 [[RESULT]], 0x3d8
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; SI: v_mov_b32_e32 [[VRESULT:v[0-9]+]], [[RESULT]]
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; SI: buffer_store_dword [[VRESULT]]
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define amdgpu_kernel void @test_add_shl_add_constant(i32 addrspace(1)* %out, [8 x i32], i32 %x, i32 %y) #0 {
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%add.0 = add i32 %x, 123
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%shl = shl i32 %add.0, 3
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%add.1 = add i32 %shl, %y
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store i32 %add.1, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}test_add_shl_add_constant_inv:
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; SI-DAG: s_load_dwordx2 s{{\[}}[[X:[0-9]+]]:[[Y:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x13
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; SI: s_lshl_b32 [[SHL3:s[0-9]+]], s[[X]], 3
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; SI: s_add_i32 [[TMP:s[0-9]+]], s[[Y]], [[SHL3]]
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; SI: s_addk_i32 [[TMP]], 0x3d8
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; SI: v_mov_b32_e32 [[VRESULT:v[0-9]+]], [[TMP]]
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; SI: buffer_store_dword [[VRESULT]]
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define amdgpu_kernel void @test_add_shl_add_constant_inv(i32 addrspace(1)* %out, [8 x i32], i32 %x, i32 %y) #0 {
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%add.0 = add i32 %x, 123
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%shl = shl i32 %add.0, 3
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%add.1 = add i32 %y, %shl
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store i32 %add.1, i32 addrspace(1)* %out, align 4
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ret void
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}
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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