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d09b64fc25
Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT. Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches. Adds a test to verify that the scheduler is working. Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP. Patch by Preston Gurd! llvm-svn: 149558
39 lines
1.6 KiB
LLVM
39 lines
1.6 KiB
LLVM
; RUN: llc < %s -mcpu=generic -mtriple=i386-apple-darwin -asm-verbose=0 | FileCheck %s
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; PR3149
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; Make sure the copy after inline asm is not coalesced away.
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; CHECK: ## InlineAsm End
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; CHECK-NEXT: BB0_2:
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; CHECK-NEXT: {{movl %esi, %eax|addl %edi, %esi}}
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@"\01LC" = internal constant [7 x i8] c"n0=%d\0A\00" ; <[7 x i8]*> [#uses=1]
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@llvm.used = appending global [1 x i8*] [ i8* bitcast (i32 (i64, i64)* @umoddi3 to i8*) ], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0]
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define i32 @umoddi3(i64 %u, i64 %v) nounwind noinline {
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entry:
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%0 = trunc i64 %v to i32 ; <i32> [#uses=2]
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%1 = trunc i64 %u to i32 ; <i32> [#uses=4]
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%2 = lshr i64 %u, 32 ; <i64> [#uses=1]
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%3 = trunc i64 %2 to i32 ; <i32> [#uses=2]
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%4 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([7 x i8]* @"\01LC", i32 0, i32 0), i32 %1) nounwind ; <i32> [#uses=0]
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%5 = icmp ult i32 %1, %0 ; <i1> [#uses=1]
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br i1 %5, label %bb2, label %bb
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bb: ; preds = %entry
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%6 = lshr i64 %v, 32 ; <i64> [#uses=1]
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%7 = trunc i64 %6 to i32 ; <i32> [#uses=1]
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%asmtmp = tail call { i32, i32 } asm "subl $5,$1\0A\09sbbl $3,$0", "=r,=&r,0,imr,1,imr,~{dirflag},~{fpsr},~{flags}"(i32 %3, i32 %7, i32 %1, i32 %0) nounwind ; <{ i32, i32 }> [#uses=2]
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%asmresult = extractvalue { i32, i32 } %asmtmp, 0 ; <i32> [#uses=1]
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%asmresult1 = extractvalue { i32, i32 } %asmtmp, 1 ; <i32> [#uses=1]
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br label %bb2
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bb2: ; preds = %bb, %entry
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%n1.0 = phi i32 [ %asmresult, %bb ], [ %3, %entry ] ; <i32> [#uses=1]
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%n0.0 = phi i32 [ %asmresult1, %bb ], [ %1, %entry ] ; <i32> [#uses=1]
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%8 = add i32 %n0.0, %n1.0 ; <i32> [#uses=1]
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ret i32 %8
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}
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declare i32 @printf(i8*, ...) nounwind
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