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9af311f3de
Add the Lanai backend to lib/Target. General Lanai backend discussion on llvm-dev thread "[RFC] Lanai backend" (http://lists.llvm.org/pipermail/llvm-dev/2016-February/095118.html). Differential Revision: http://reviews.llvm.org/D17011 llvm-svn: 264578
65 lines
2.2 KiB
TableGen
65 lines
2.2 KiB
TableGen
//===- LanaiRegisterInfo.td - Lanai Register defs ------------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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// Declarations that describe the Lanai register file
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//===----------------------------------------------------------------------===//
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// Registers are identified with 5-bit ID numbers.
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class LanaiReg<bits<5> num, string n, list<Register> subregs = [],
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list<string> altNames = []> : Register<n, altNames> {
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field bits<5> Num;
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let Num = num;
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let Namespace = "Lanai";
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let SubRegs = subregs;
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}
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let Namespace = "Lanai" in {
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def sub_32 : SubRegIndex<32>;
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}
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// Integer registers
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foreach i = 0-31 in {
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def R#i : LanaiReg<i, "r"#i>, DwarfRegNum<[i]>;
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}
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// Register aliases
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let SubRegIndices = [sub_32] in {
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def PC : LanaiReg< 2, "pc", [R2]>, DwarfRegAlias<R2>;
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def SP : LanaiReg< 4, "sp", [R4]>, DwarfRegAlias<R4>;
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def FP : LanaiReg< 5, "fp", [R5]>, DwarfRegAlias<R5>;
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def RV : LanaiReg< 8, "rv", [R8]>, DwarfRegAlias<R8>;
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def RR1 : LanaiReg<10, "rr1", [R10]>, DwarfRegAlias<R10>;
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def RR2 : LanaiReg<11, "rr2", [R11]>, DwarfRegAlias<R11>;
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def RCA : LanaiReg<15, "rca", [R15]>, DwarfRegAlias<R15>;
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}
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// Define a status register to capture the dependencies between the set flag
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// and setcc instructions
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def SR : LanaiReg< 0, "sw">;
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// Register classes.
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def GPR : RegisterClass<"Lanai", [i32], 32,
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(add R3, R9, R12, R13, R14, R16, R17,
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(sequence "R%i", 20, 31),
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R6, R7, R18, R19, // registers for passing arguments
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R15, RCA, // register for constant addresses
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R10, RR1, R11, RR2, // programmer controlled registers
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R8, RV, // return value
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R5, FP, // frame pointer
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R4, SP, // stack pointer
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R2, PC, // program counter
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R1, // all 1s (0xffffffff)
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R0 // constant 0
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)>;
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// Condition code register class
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def CCR : RegisterClass<"Lanai", [i32], 32, (add SR)> {
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let CopyCost = -1; // Don't allow copying of status registers
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let isAllocatable = 0;
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}
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