mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-23 13:02:52 +02:00
2b52d3cc02
This patch implements two changes:
- Move processor feature definition into a new file SystemZFeatures.td,
and provide explicit lists of supported and unsupported features for
each level of the z/Architecture. This allows specifying unsupported
features in the scheduler definition files for each processor.
- Add optional aliases for the -mcpu processor names according to the
level of the z/Architecture, for compatibility with other compilers
on the platform. The supported aliases are:
-mcpu=arch8 equals -mcpu=z10
-mcpu=arch9 equals -mcpu=z196
-mcpu=arch10 equals -mcpu=zEC12
-mcpu=arch11 equals -mcpu=z13
llvm-svn: 285577
76 lines
2.7 KiB
TableGen
76 lines
2.7 KiB
TableGen
//===-- SystemZ.td - Describe the SystemZ target machine -----*- tblgen -*-===//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file is distributed under the University of Illinois Open Source
|
|
// License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Target-independent interfaces which we are implementing
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
include "llvm/Target/Target.td"
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// SystemZ subtarget features
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
include "SystemZFeatures.td"
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// SystemZ subtarget scheduling models
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
include "SystemZSchedule.td"
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// SystemZ supported processors
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
include "SystemZProcessors.td"
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Register file description
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
include "SystemZRegisterInfo.td"
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Calling convention description
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
include "SystemZCallingConv.td"
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Instruction descriptions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
include "SystemZOperators.td"
|
|
include "SystemZOperands.td"
|
|
include "SystemZPatterns.td"
|
|
include "SystemZInstrFormats.td"
|
|
include "SystemZInstrInfo.td"
|
|
include "SystemZInstrVector.td"
|
|
include "SystemZInstrFP.td"
|
|
|
|
def SystemZInstrInfo : InstrInfo {}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Assembly parser
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
def SystemZAsmParser : AsmParser {
|
|
let ShouldEmitMatchRegisterName = 0;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Top-level target declaration
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
def SystemZ : Target {
|
|
let InstructionSet = SystemZInstrInfo;
|
|
let AssemblyParsers = [SystemZAsmParser];
|
|
}
|