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76f7fdd9e3
This introduce basic tablegen infra such as CSKY{InstrFormats,InstrInfo,RegisterInfo,}.td.
For now, only add instruction definitions for basic CSKY ISA operations, and the instruction format and register info are almost complete.
Our initial target is a working MC layer rather than codegen, so appropriate SelectionDAG patterns will come later.
Differential Revision: https://reviews.llvm.org/D89180
529 lines
18 KiB
TableGen
529 lines
18 KiB
TableGen
//===-- CSKYInstrFormats.td - CSKY Instruction Formats -----*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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class AddrMode<bits<5> val> {
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bits<5> Value = val;
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}
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def AddrModeNone : AddrMode<0>;
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def AddrMode32B : AddrMode<1>; // ld32.b, ld32.bs, st32.b, st32.bs, +4kb
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def AddrMode32H : AddrMode<2>; // ld32.h, ld32.hs, st32.h, st32.hs, +8kb
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def AddrMode32WD : AddrMode<3>; // ld32.w, st32.w, ld32.d, st32.d, +16kb
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def AddrMode16B : AddrMode<4>; // ld16.b, +32b
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def AddrMode16H : AddrMode<5>; // ld16.h, +64b
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def AddrMode16W : AddrMode<6>; // ld16.w, +128b or +1kb
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def AddrMode32SDF : AddrMode<7>; // flds, fldd, +1kb
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class CSKYInst<AddrMode am, int sz, dag outs, dag ins, string asmstr,
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list<dag> pattern> : Instruction {
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let Namespace = "CSKY";
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int Size = sz;
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AddrMode AM = am;
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let OutOperandList = outs;
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let InOperandList = ins;
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let AsmString = asmstr;
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let Pattern = pattern;
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let Itinerary = NoItinerary;
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let TSFlags{4 - 0} = AM.Value;
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}
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class CSKYPseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
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: CSKYInst<AddrModeNone, 0, outs, ins, asmstr, pattern> {
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let isCodeGenOnly = 1;
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let isPseudo = 1;
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}
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class CSKY32Inst<AddrMode am, bits<6> opcode, dag outs, dag ins, string asmstr,
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list<dag> pattern>
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: CSKYInst<am, 4, outs, ins, asmstr, pattern> {
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field bits<32> Inst;
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let Inst{31 - 26} = opcode;
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}
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// CSKY 32-bit instruction
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// Format< OP[6] | Offset[26] >
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// Instruction(1): bsr32
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class J<bits<6> opcode, dag outs, dag ins, string op, list<dag> pattern>
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: CSKY32Inst<AddrModeNone, opcode, outs, ins, !strconcat(op, "\t$offset"),
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pattern> {
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bits<26> offset;
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let Inst{25 - 0} = offset;
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}
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// Format< OP[6] | RZ[5] | SOP[3] | OFFSET[18] >
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// Instructions(7): grs, lrs32.b, lrs32.h, lrs32.w, srs32.b, srs32.h, srs32.w
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class I_18_Z_L<bits<3> sop, string op, Operand operand, list<dag> pattern>
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: CSKY32Inst<AddrModeNone, 0x33, (outs GPR:$rz), (ins operand:$offset),
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!strconcat(op, "\t$rz, $offset"), pattern> {
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bits<5> rz;
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bits<18> offset;
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let Inst{25 - 21} = rz;
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let Inst{20 - 18} = sop;
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let Inst{17 - 0} = offset;
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}
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// Format< OP[6] | RZ[5] | RX[5] | IMM[16] >
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// Instructions(1): ori32
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class I_16_ZX<string op, ImmLeaf ImmType, list<dag> pattern>
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: CSKY32Inst<AddrModeNone, 0x3b,
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(outs GPR:$rz), (ins GPR:$rx,ImmType:$imm16),
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!strconcat(op, "\t$rz, $rx, $imm16"), pattern> {
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bits<5> rz;
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bits<5> rx;
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bits<16> imm16;
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let Inst{25 - 21} = rz;
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let Inst{20 - 16} = rx;
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let Inst{15 - 0} = imm16;
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}
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// Format< OP[6] | SOP[5] | RZ[5] | IMM[16] >
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// Instructions(3): movi32, movih32, (bgeni32)
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class I_16_MOV<bits<5> sop, string op, ImmLeaf ImmType>
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: CSKY32Inst<AddrModeNone, 0x3a, (outs GPR:$rz), (ins ImmType:$imm16),
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!strconcat(op, "\t$rz, $imm16"),
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[(set GPR:$rz, ImmType:$imm16)]> {
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bits<5> rz;
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bits<16> imm16;
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let Inst{25 - 21} = sop;
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let Inst{20 - 16} = rz;
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let Inst{15 - 0} = imm16;
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let isReMaterializable = 1;
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let isAsCheapAsAMove = 1;
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let isMoveImm = 1;
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}
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// Format< OP[6] | SOP[5] | RZ[5] | OFFSET[16] >
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// Instructions(1): lrw32
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class I_16_Z_L<bits<5> sop, string op, Operand operand, list<dag> pattern>
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: CSKY32Inst<AddrModeNone, 0x3a,
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(outs GPR:$rz), (ins operand:$imm16),
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!strconcat(op, "\t$rz, [$imm16]"), pattern> {
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bits<5> rz;
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bits<16> imm16;
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let Inst{25 - 21} = sop;
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let Inst{20 - 16} = rz;
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let Inst{15 - 0} = imm16;
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}
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// Format< OP[6] | SOP[5] | 00000[5] | OFFSET[16] >
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// Instructions(5): bt32, bf32, br32, jmpi32, jsri32
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class I_16_L<bits<5> sop, dag outs, dag ins, string op, list<dag> pattern>
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: CSKY32Inst<AddrModeNone, 0x3a, outs, ins, !strconcat(op, "\t$imm16"),
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pattern> {
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bits<16> imm16;
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let Inst{25 - 21} = sop;
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let Inst{20 - 16} = 0;
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let Inst{15 - 0} = imm16;
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}
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// bt32, bf32, br32, jmpi32
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class I_16_L_B<bits<5> sop, string op, Operand operand, list<dag> pattern>
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: I_16_L<sop, (outs), (ins operand:$imm16, CARRY:$ca), op, pattern> {
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let isBranch = 1;
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let isTerminator = 1;
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}
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// Format< OP[6] | SOP[5] | RX[5] | 0000000000000000[16] >
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// Instructions(2): jmp32, jsr32
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class I_16_JX<bits<5> sop, string op, list<dag> pattern>
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: CSKY32Inst<AddrModeNone, 0x3a, (outs), (ins GPR:$rx),
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!strconcat(op, "\t$rx"), pattern> {
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bits<5> rx;
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bits<16> imm16;
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let Inst{25 - 21} = sop;
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let Inst{20 - 16} = rx;
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let Inst{15 - 0} = 0;
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}
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// Format< OP[6] | SOP[5] | RX[5] | 00000000000000[14] | IMM[2] >
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// Instructions(1): jmpix32
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class I_16_J_XI<bits<5> sop, string op, Operand operand, list<dag> pattern>
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: CSKY32Inst<AddrModeNone, 0x3a, (outs),
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(ins GPR:$rx, operand:$imm2),
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!strconcat(op, "\t$rx, $imm2"), pattern> {
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bits<5> rx;
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bits<2> imm2;
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let Inst{25 - 21} = sop;
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let Inst{20 - 16} = rx;
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let Inst{15 - 2} = 0;
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let Inst{1 - 0} = imm2;
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}
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// Format< OP[6] | SOP[5] | PCODE[5] | 0000000000000000[16] >
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// Instructions(1): rts32
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class I_16_RET<bits<5> sop, bits<5> pcode, string op, list<dag> pattern>
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: CSKY32Inst<AddrModeNone, 0x3a, (outs), (ins), op, pattern> {
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let Inst{25 - 21} = sop;
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let Inst{20 - 16} = pcode;
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let Inst{15 - 0} = 0;
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let isTerminator = 1;
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let isReturn = 1;
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let isBarrier = 1;
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}
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// Format< OP[6] | SOP[5] | RX[5] | IMM16[16] >
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// Instructions(3): cmpnei32, cmphsi32, cmplti32
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class I_16_X<bits<5> sop, string op>
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: CSKY32Inst<AddrModeNone, 0x3a, (outs CARRY:$ca),
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(ins GPR:$rx, i32imm:$imm16), !strconcat(op, "\t$rx, $imm16"), []> {
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bits<16> imm16;
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bits<5> rx;
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let Inst{25 - 21} = sop;
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let Inst{20 - 16} = rx;
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let Inst{15 - 0} = imm16;
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let isCompare = 1;
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}
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// Format< OP[6] | SOP[5] | RX[5] | OFFSET[16] >
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// Instructions(7): bez32, bnez32, bnezad32, bhz32, blsz32, blz32, bhsz32
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class I_16_X_L<bits<5> sop, string op, Operand operand>
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: CSKY32Inst<AddrModeNone, 0x3a, (outs), (ins GPR:$rx, operand:$imm16),
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!strconcat(op, "\t$rx, $imm16"), []> {
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bits<5> rx;
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bits<16> imm16;
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let Inst{25 - 21} = sop;
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let Inst{20 - 16} = rx;
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let Inst{15 - 0} = imm16;
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let isBranch = 1;
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let isTerminator = 1;
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}
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// Format< OP[6] | RZ[5] | RX[5] | SOP[4] | IMM[12] >
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// Instructions(5): addi32, subi32, andi32, andni32, xori32
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class I_12<bits<4> sop, string op, SDNode node, ImmLeaf ImmType>
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: CSKY32Inst<AddrModeNone, 0x39, (outs GPR:$rz),
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(ins GPR:$rx, ImmType:$imm12), !strconcat(op, "\t$rz, $rx, $imm12"),
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[(set GPR:$rz, (node GPR:$rx, ImmType:$imm12))]> {
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bits<5> rz;
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bits<5> rx;
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bits<12> imm12;
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let Inst{25 - 21} = rz;
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let Inst{20 - 16} = rx;
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let Inst{15 - 12} = sop;
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let Inst{11 - 0} = imm12;
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}
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class I_LDST<AddrMode am, bits<6> opcode, bits<4> sop, dag outs, dag ins,
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string op, list<dag> pattern>
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: CSKY32Inst<am, opcode, outs, ins, !strconcat(op, "\t$rz, ($rx, $imm12)"),
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pattern> {
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bits<5> rx;
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bits<5> rz;
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bits<12> imm12;
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let Inst{25 - 21} = rz;
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let Inst{20 - 16} = rx;
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let Inst{15 - 12} = sop;
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let Inst{11 - 0} = imm12;
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}
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// Format< OP[6] | RZ[5] | RX[5] | SOP[4] | OFFSET[12] >
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// Instructions(6): ld32.b, ld32.bs, ld32.h, ld32.hs, ld32.w, ld32.d
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class I_LD<AddrMode am, bits<4> sop, string op, Operand operand>
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: I_LDST<am, 0x36, sop,
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(outs GPR:$rz), (ins GPR:$rx, operand:$imm12), op, []>;
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// Format< OP[6] | RZ[5] | RX[5] | SOP[4] | OFFSET[12] >
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// Instructions(4): st32.b, st32.h, st32.w, st32.d
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class I_ST<AddrMode am, bits<4> sop, string op, Operand operand>
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: I_LDST<am, 0x37, sop, (outs),
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(ins GPR:$rz, GPR:$rx, operand:$imm12), op, []>;
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// Format< OP[6] | SOP[5] | PCODE[5] | 0000[4] | 000 | R28 | LIST2[3] | R15 |
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// LIST1[4] >
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// Instructions(2): push32, pop32
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class I_12_PP<bits<5> sop, bits<5> pcode, dag outs, dag ins, string op>
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: CSKY32Inst<AddrModeNone, 0x3a, outs, ins, !strconcat(op, "\t$regs"), []> {
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bits<12> regs;
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let Inst{25 - 21} = sop;
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let Inst{20 - 16} = pcode;
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let Inst{15 - 12} = 0;
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let Inst{11 - 0} = regs;
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}
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// Format< OP[6] | RZ[5] | RX[5] | SOP[6] | PCODE[5] | IMM[5]>
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// Instructions(4): incf32, inct32, decf32, dect32
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class I_5_ZX<bits<6> sop, bits<5> pcode, string op, ImmLeaf ImmType,
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list<dag> pattern>
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: CSKY32Inst<AddrModeNone, 0x31, (outs GPR:$rz),
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(ins GPR:$false, GPR:$rx, ImmType:$imm5),
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!strconcat(op, "\t$rz, $rx, $imm5"), pattern> {
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bits<5> rz;
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bits<5> rx;
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bits<5> imm5;
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let Inst{25 - 21} = rz;
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let Inst{20 - 16} = rx;
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let Inst{15 - 10} = sop;
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let Inst{9 - 5} = pcode;
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let Inst{4 - 0} = imm5;
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let Constraints = "$rz = $false";
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}
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// Format< OP[6] | IMM[5] | RX[5] | SOP[6] | PCODE[5] | RZ[5]>
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// Instructions(13): decgt32, declt32, decne32, lsli32, lslc32, lsri32
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// lsrc32, asri32, asrc32, rotli32, xsr32, bclri32, bseti32
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class I_5_XZ<bits<6> sop, bits<5> pcode, string op, dag ins, dag outs,
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list<dag> pattern>
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: CSKY32Inst<AddrModeNone, 0x31, ins, outs,
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!strconcat(op, "\t$rz, $rx, $imm5"), pattern> {
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bits<5> imm5;
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bits<5> rx;
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bits<5> rz;
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let Inst{25 - 21} = imm5;
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let Inst{20 - 16} = rx;
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let Inst{15 - 10} = sop;
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let Inst{9 - 5} = pcode;
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let Inst{4 - 0} = rz;
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}
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// Format< OP[6] | RY[5] | RX[5] | SOP[6] | PCODE[5] | IMM[5]>
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// Instructions(2): ldm32, (ldq32), stm32, (stq32)
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class I_5_YX<bits<6> opcode, dag outs, dag ins, string op, list<dag> pattern,
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bits<5> imm5>
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: CSKY32Inst<AddrModeNone, opcode, outs, ins,
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op #"\t${ry}, (${rx}), " #!cast<int>(imm5), pattern> {
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bits<5> rx;
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bits<5> ry;
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let Inst{25 - 21} = ry; // ry
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let Inst{20 - 16} = rx;
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let Inst{15 - 10} = 0b000111;
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let Inst{9 - 5} = 0b00001;
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let Inst{4 - 0} = imm5{4 - 0}; // imm5
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}
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// Format< OP[6] | LSB[5] | RX[5] | SOP[6] | MSB[5] | RZ[5]>
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// Instructions(6): zext32, zextb32, zexth32, sext32, sextb32, sexth32
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class I_5_XZ_U<bits<6> sop, bits<5> lsb, bits<5> msb, dag outs, dag ins,
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string op, list<dag> pattern>
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: CSKY32Inst<AddrModeNone, 0x31, outs, ins,
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op #"\t$rz, $rx, " #!cast<int>(msb) #", " #!cast<int>(lsb),
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pattern> {
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bits<5> rx;
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bits<5> rz;
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let Inst{25 - 21} = lsb; // lsb
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let Inst{20 - 16} = rx;
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let Inst{15 - 10} = sop;
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let Inst{9 - 5} = msb; // msb
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let Inst{4 - 0} = rz;
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}
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// sextb, sexth
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class I_5_XZ_US<bits<6> sop, bits<5> lsb, bits<5> msb, string op, SDNode opnode,
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ValueType type> : I_5_XZ_U<sop, lsb, msb,
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(outs GPR:$rz), (ins GPR:$rx),op, [(set GPR:$rz, (opnode GPR:$rx, type))]>;
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class I_5_XZ_UZ<bits<6> sop, bits<5> lsb, bits<5> msb, string op, int v>
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: I_5_XZ_U<sop, lsb, msb, (outs GPR:$rz), (ins GPR:$rx), op,
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[(set GPR:$rz, (and GPR:$rx, (i32 v)))]>;
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// Format< OP[6] | RZ[5] | RX[5] | SOP[6] | SIZE[5] | LSB[5]>
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// Instructions(1): ins32
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class I_5_ZX_U<bits<6> sop, string op, Operand operand, list<dag> pattern>
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: CSKY32Inst<AddrModeNone, 0x31, (outs GPR:$rz), (ins operand:$size_lsb),
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!strconcat(op, "\t$rz, operand:$size_lsb"), pattern> {
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bits<10> size_lsb;
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bits<5> rz;
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bits<5> rx;
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let Inst{25 - 21} = rz;
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let Inst{20 - 16} = rx;
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let Inst{15 - 10} = sop;
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let Inst{9 - 5} = size_lsb{9 - 5}; // size
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let Inst{4 - 0} = size_lsb{4 - 0}; // lsb
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}
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// Format< OP[6] | IMM[5] | RX[5] | SOP[6] | PCODE[5] | 00000 >
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// Instructions(1): btsti32
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class I_5_X<bits<6> sop, bits<5> pcode, string op, ImmLeaf ImmType,
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list<dag> pattern>
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: CSKY32Inst<AddrModeNone, 0x31,
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(outs CARRY:$ca), (ins GPR:$rx, ImmType:$imm5),
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!strconcat(op, "\t$rx, $imm5"), pattern> {
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bits<5> imm5;
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bits<5> rx;
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let Inst{25 - 21} = imm5;
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let Inst{20 - 16} = rx;
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let Inst{15 - 10} = sop;
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let Inst{9 - 5} = pcode;
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let Inst{4 - 0} = 0;
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let isCompare = 1;
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}
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// Format< OP[6] | IMM[5] | 00000[5] | SOP[6] | PCODE[5] | RZ[5]>
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// Instructions(1): bmaski32
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class I_5_Z<bits<6> sop, bits<5> pcode, string op, ImmLeaf ImmType,
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list<dag> pattern>
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: CSKY32Inst<AddrModeNone, 0x31, (outs GPR:$rz), (ins ImmType:$imm5),
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!strconcat(op, "\t$rz, $imm5"), pattern> {
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bits<5> imm5;
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bits<5> rz;
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let Inst{25 - 21} = imm5;
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let Inst{20 - 16} = 0;
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let Inst{15 - 10} = sop;
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let Inst{9 - 5} = pcode;
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let Inst{4 - 0} = rz;
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}
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// Format< OP[6] | RY[5] | RX[5] | SOP[6] | PCODE[5] | RZ[5] >
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// Instructions(24): addu32, addc32, subu32, subc32, (rsub32), ixh32, ixw32,
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// ixd32, and32, andn32, or32, xor32, nor32, lsl32, lsr32, asr32, rotl32
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// mult32, divu32, divs32, mul.(u/s)32, mula.32.l, mula.u32, mulall.s16.s
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class R_YXZ<bits<6> opcode, bits<6> sop, bits<5> pcode, dag outs, dag ins,
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string op, list<dag> pattern>
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: CSKY32Inst<AddrModeNone, opcode, outs, ins,
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!strconcat(op, "\t$rz, $rx, $ry"), pattern> {
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bits<5> ry;
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bits<5> rx;
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bits<5> rz;
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let Inst{25 - 21} = ry;
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let Inst{20 - 16} = rx;
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let Inst{15 - 10} = sop;
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let Inst{9 - 5} = pcode;
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let Inst{4 - 0} = rz;
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}
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// R_YXZ instructions with simple pattern
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// Output: GPR:rz
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// Input: GPR:rx, GPR:ry
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// Asm string: op rz, rx, ry
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// Instructions: addu32, subu32, ixh32, ixw32, ixd32, and32, andn32, or32,
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// xor32, nor32, lsl32, lsr32, asr32, mult32, divu32, divs32
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class R_YXZ_SP_F1<bits<6> sop, bits<5> pcode, PatFrag opnode, string op,
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bit Commutable = 0> : R_YXZ<0x31, sop, pcode, (outs GPR:$rz),
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(ins GPR:$rx, GPR:$ry), op, [(set GPR:$rz, (opnode GPR:$rx, GPR:$ry))]> {
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let isCommutable = Commutable;
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}
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// Format< OP[6] | RY[5] | RX[5] | SOP[6] | PCODE[5] | RZ[5] >
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// Instructions:(8) ldr32.b, ldr32.h, ldr32.bs, ldr32.hs, ldr32.w,
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// str32.b, str32.h, str32.w
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class R_YXZ_LDST<bits<6> opcode, bits<6> sop, bits<5> pcode, int no, dag outs,
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dag ins, string op, list<dag> pattern>
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: CSKY32Inst<AddrModeNone, opcode, outs, ins,
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op #"\t$rz, ($rx, $ry << " #no #")", pattern> {
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bits<5> rx;
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bits<5> ry;
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bits<5> rz;
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let Inst{25 - 21} = ry; // ry;
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let Inst{20 - 16} = rx; // rx;
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let Inst{15 - 10} = sop;
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let Inst{9 - 5} = pcode; // pcode;
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let Inst{4 - 0} = rz;
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}
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class I_LDR<bits<6> sop, bits<5> pcode, string op, int no>
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: R_YXZ_LDST<0x34, sop, pcode, no,
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(outs GPR:$rz), (ins GPR:$rx, GPR:$ry), op, []>;
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class I_STR<bits<6> sop, bits<5> pcode, string op, int no>
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: R_YXZ_LDST<0x35, sop, pcode, no, (outs),
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(ins GPR:$rz, GPR:$rx, GPR:$ry), op, []>;
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// Format< OP[6] | RX[5] | RX[5] | SOP[6] | PCODE[5] | RZ[5] >
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// Instructions:(1) not32
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class R_XXZ<bits<6> sop, bits<5> pcode, dag outs, dag ins, string op,
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list<dag> pattern>
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: CSKY32Inst<AddrModeNone, 0x31, outs, ins, !strconcat(op, "\t$rz, $rx"),
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pattern> {
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bits<5> rx;
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bits<5> rz;
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let Inst{25 - 21} = rx;
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let Inst{20 - 16} = rx;
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let Inst{15 - 10} = sop;
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let Inst{9 - 5} = pcode;
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let Inst{4 - 0} = rz;
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}
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// Format< OP[6] | RY[5] | RX[5] | SOP[6] | PCODE[5] | 00000[5] >
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// Instructions:(4) cmpne32, cmphs32, cmplt32, tst32
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class R_YX<bits<6> sop, bits<5> pcode, string op>
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: CSKY32Inst<AddrModeNone, 0x31, (outs CARRY:$ca),
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(ins GPR:$rx, GPR:$ry),
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!strconcat(op, "\t$rx, $ry"), []> {
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bits<5> ry;
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bits<5> rx;
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let Inst{25 - 21} = ry;
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let Inst{20 - 16} = rx;
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let Inst{15 - 10} = sop;
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let Inst{9 - 5} = pcode;
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let Inst{4 - 0} = 0;
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let isCompare = 1;
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}
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// Format< OP[6] | 00000[5] | RX[5] | SOP[6] | PCODE[5] | RZ[5] >
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// Instructions:(12)
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// mov32, xtrb0.32, xtrb1.32, xtrb2.32, xtrb3.32, brev32, revb32
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// revh32, abs32, ff0.32, ff1.32, bgenr32
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class R_XZ<bits<6> sop, bits<5> pcode, string op>
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: CSKY32Inst<AddrModeNone, 0x31, (outs GPR:$rz), (ins GPR:$rx),
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!strconcat(op, "\t$rz, $rx"), []> {
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bits<5> rx;
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bits<5> rz;
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let Inst{25 - 21} = 0;
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let Inst{20 - 16} = rx;
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let Inst{15 - 10} = sop;
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let Inst{9 - 5} = pcode;
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let Inst{4 - 0} = rz;
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}
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// Format< OP[6] | RZ[5] | RX[5] | SOP[6] | PCODE[5] | 00000[5] >
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// Instructions:(2) movf32, movt32
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class R_ZX<bits<6> sop, bits<5> pcode, string op, list<dag> pattern>
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: CSKY32Inst<AddrModeNone, 0x31, (outs GPR:$rz),
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(ins CARRY:$ca, GPR:$rx, GPR:$false),
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!strconcat(op, "\t$rz, $rx"), pattern> {
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bits<5> rz;
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bits<5> rx;
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let Inst{25 - 21} = rz;
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let Inst{20 - 16} = rx;
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let Inst{15 - 10} = sop;
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let Inst{9 - 5} = pcode;
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let Inst{4 - 0} = 0;
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let Constraints = "$rz = $false";
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let isSelect = 1;
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}
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// Format< OP[6] | 00000[5] | RX[5] | SOP[6] | PCODE[5] | 00000[5] >
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// Instructions:(1) tstnbz32
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class R_X<bits<6> sop, bits<5> pcode, string op, list<dag> pattern>
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: CSKY32Inst<AddrModeNone, 0x31, (outs CARRY:$ca),(ins GPR:$rx),
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!strconcat(op, "\t$rx"), pattern> {
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bits<5> rx;
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let Inst{25 - 21} = 0;
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let Inst{20 - 16} = rx;
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let Inst{15 - 10} = sop;
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let Inst{9 - 5} = pcode;
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let Inst{4 - 0} = 0;
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}
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// Format< OP[6] | 00000[5] | 00000[5] | SOP[6] | PCODE[5] | RZ[5] >
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// Instructions:(2) mvc32, mvcv32
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class R_Z_1<bits<6> sop, bits<5> pcode, string op>
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: CSKY32Inst<AddrModeNone, 0x31, (outs GPR:$rz),
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(ins CARRY:$ca), !strconcat(op, "\t$rz"), []> {
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bits<5> rz;
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let Inst{25 - 21} = 0;
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let Inst{20 - 16} = 0;
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let Inst{15 - 10} = sop;
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let Inst{9 - 5} = pcode;
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let Inst{4 - 0} = rz;
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}
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// Format< OP[6] | RZ[5] | 00000[5] | SOP[6] | PCODE[5] | 00000[5] >
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// Instructions:(2) clrf32, clrt32
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class R_Z_2<bits<6> sop, bits<5> pcode, string op, list<dag> pattern>
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: CSKY32Inst<AddrModeNone, 0x31, (outs GPR:$rz),
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(ins CARRY:$ca, GPR:$false), !strconcat(op, "\t$rz"), []> {
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bits<5> rz;
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let Inst{25 - 21} = rz;
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let Inst{20 - 16} = 0;
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let Inst{15 - 10} = sop;
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let Inst{9 - 5} = pcode;
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let Inst{4 - 0} = 0;
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let Constraints = "$rz = $false";
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}
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