mirror of
https://github.com/RPCS3/llvm-mirror.git
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6924e02442
Reviewers: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, tony-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D25577 llvm-svn: 285359
434 lines
13 KiB
C++
434 lines
13 KiB
C++
//===-- AMDGPUBaseInfo.cpp - AMDGPU Base encoding information--------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPUBaseInfo.h"
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#include "AMDGPU.h"
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#include "SIDefines.h"
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#include "llvm/IR/LLVMContext.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/GlobalValue.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCSectionELF.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/MC/SubtargetFeature.h"
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#define GET_SUBTARGETINFO_ENUM
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#include "AMDGPUGenSubtargetInfo.inc"
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#undef GET_SUBTARGETINFO_ENUM
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#define GET_REGINFO_ENUM
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#include "AMDGPUGenRegisterInfo.inc"
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#undef GET_REGINFO_ENUM
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#define GET_INSTRINFO_NAMED_OPS
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#define GET_INSTRINFO_ENUM
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#include "AMDGPUGenInstrInfo.inc"
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#undef GET_INSTRINFO_NAMED_OPS
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#undef GET_INSTRINFO_ENUM
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namespace {
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/// \returns Bit mask for given bit \p Shift and bit \p Width.
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unsigned getBitMask(unsigned Shift, unsigned Width) {
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return ((1 << Width) - 1) << Shift;
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}
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/// \brief Packs \p Src into \p Dst for given bit \p Shift and bit \p Width.
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///
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/// \returns Packed \p Dst.
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unsigned packBits(unsigned Src, unsigned Dst, unsigned Shift, unsigned Width) {
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Dst &= ~(1 << Shift) & ~getBitMask(Shift, Width);
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Dst |= (Src << Shift) & getBitMask(Shift, Width);
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return Dst;
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}
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/// \brief Unpacks bits from \p Src for given bit \p Shift and bit \p Width.
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///
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/// \returns Unpacked bits.
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unsigned unpackBits(unsigned Src, unsigned Shift, unsigned Width) {
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return (Src & getBitMask(Shift, Width)) >> Shift;
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}
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/// \returns Vmcnt bit shift.
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unsigned getVmcntBitShift() { return 0; }
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/// \returns Vmcnt bit width.
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unsigned getVmcntBitWidth() { return 4; }
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/// \returns Expcnt bit shift.
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unsigned getExpcntBitShift() { return 4; }
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/// \returns Expcnt bit width.
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unsigned getExpcntBitWidth() { return 3; }
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/// \returns Lgkmcnt bit shift.
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unsigned getLgkmcntBitShift() { return 8; }
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/// \returns Lgkmcnt bit width.
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unsigned getLgkmcntBitWidth() { return 4; }
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} // anonymous namespace
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namespace llvm {
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namespace AMDGPU {
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IsaVersion getIsaVersion(const FeatureBitset &Features) {
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if (Features.test(FeatureISAVersion7_0_0))
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return {7, 0, 0};
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if (Features.test(FeatureISAVersion7_0_1))
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return {7, 0, 1};
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if (Features.test(FeatureISAVersion7_0_2))
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return {7, 0, 2};
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if (Features.test(FeatureISAVersion8_0_0))
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return {8, 0, 0};
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if (Features.test(FeatureISAVersion8_0_1))
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return {8, 0, 1};
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if (Features.test(FeatureISAVersion8_0_2))
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return {8, 0, 2};
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if (Features.test(FeatureISAVersion8_0_3))
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return {8, 0, 3};
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if (Features.test(FeatureISAVersion8_0_4))
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return {8, 0, 4};
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if (Features.test(FeatureISAVersion8_1_0))
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return {8, 1, 0};
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return {0, 0, 0};
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}
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void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header,
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const FeatureBitset &Features) {
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IsaVersion ISA = getIsaVersion(Features);
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memset(&Header, 0, sizeof(Header));
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Header.amd_kernel_code_version_major = 1;
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Header.amd_kernel_code_version_minor = 0;
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Header.amd_machine_kind = 1; // AMD_MACHINE_KIND_AMDGPU
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Header.amd_machine_version_major = ISA.Major;
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Header.amd_machine_version_minor = ISA.Minor;
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Header.amd_machine_version_stepping = ISA.Stepping;
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Header.kernel_code_entry_byte_offset = sizeof(Header);
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// wavefront_size is specified as a power of 2: 2^6 = 64 threads.
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Header.wavefront_size = 6;
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// These alignment values are specified in powers of two, so alignment =
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// 2^n. The minimum alignment is 2^4 = 16.
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Header.kernarg_segment_alignment = 4;
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Header.group_segment_alignment = 4;
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Header.private_segment_alignment = 4;
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}
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MCSection *getHSATextSection(MCContext &Ctx) {
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return Ctx.getELFSection(".hsatext", ELF::SHT_PROGBITS,
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ELF::SHF_ALLOC | ELF::SHF_WRITE |
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ELF::SHF_EXECINSTR |
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ELF::SHF_AMDGPU_HSA_AGENT |
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ELF::SHF_AMDGPU_HSA_CODE);
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}
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MCSection *getHSADataGlobalAgentSection(MCContext &Ctx) {
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return Ctx.getELFSection(".hsadata_global_agent", ELF::SHT_PROGBITS,
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ELF::SHF_ALLOC | ELF::SHF_WRITE |
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ELF::SHF_AMDGPU_HSA_GLOBAL |
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ELF::SHF_AMDGPU_HSA_AGENT);
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}
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MCSection *getHSADataGlobalProgramSection(MCContext &Ctx) {
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return Ctx.getELFSection(".hsadata_global_program", ELF::SHT_PROGBITS,
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ELF::SHF_ALLOC | ELF::SHF_WRITE |
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ELF::SHF_AMDGPU_HSA_GLOBAL);
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}
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MCSection *getHSARodataReadonlyAgentSection(MCContext &Ctx) {
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return Ctx.getELFSection(".hsarodata_readonly_agent", ELF::SHT_PROGBITS,
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ELF::SHF_ALLOC | ELF::SHF_AMDGPU_HSA_READONLY |
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ELF::SHF_AMDGPU_HSA_AGENT);
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}
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bool isGroupSegment(const GlobalValue *GV) {
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return GV->getType()->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS;
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}
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bool isGlobalSegment(const GlobalValue *GV) {
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return GV->getType()->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS;
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}
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bool isReadOnlySegment(const GlobalValue *GV) {
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return GV->getType()->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS;
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}
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bool shouldEmitConstantsToTextSection(const Triple &TT) {
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return TT.getOS() != Triple::AMDHSA;
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}
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int getIntegerAttribute(const Function &F, StringRef Name, int Default) {
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Attribute A = F.getFnAttribute(Name);
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int Result = Default;
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if (A.isStringAttribute()) {
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StringRef Str = A.getValueAsString();
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if (Str.getAsInteger(0, Result)) {
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LLVMContext &Ctx = F.getContext();
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Ctx.emitError("can't parse integer attribute " + Name);
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}
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}
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return Result;
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}
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std::pair<int, int> getIntegerPairAttribute(const Function &F,
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StringRef Name,
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std::pair<int, int> Default,
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bool OnlyFirstRequired) {
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Attribute A = F.getFnAttribute(Name);
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if (!A.isStringAttribute())
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return Default;
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LLVMContext &Ctx = F.getContext();
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std::pair<int, int> Ints = Default;
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std::pair<StringRef, StringRef> Strs = A.getValueAsString().split(',');
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if (Strs.first.trim().getAsInteger(0, Ints.first)) {
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Ctx.emitError("can't parse first integer attribute " + Name);
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return Default;
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}
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if (Strs.second.trim().getAsInteger(0, Ints.second)) {
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if (!OnlyFirstRequired || Strs.second.trim().size()) {
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Ctx.emitError("can't parse second integer attribute " + Name);
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return Default;
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}
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}
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return Ints;
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}
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unsigned getWaitcntBitMask(IsaVersion Version) {
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unsigned Vmcnt = getBitMask(getVmcntBitShift(), getVmcntBitWidth());
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unsigned Expcnt = getBitMask(getExpcntBitShift(), getExpcntBitWidth());
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unsigned Lgkmcnt = getBitMask(getLgkmcntBitShift(), getLgkmcntBitWidth());
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return Vmcnt | Expcnt | Lgkmcnt;
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}
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unsigned getVmcntBitMask(IsaVersion Version) {
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return (1 << getVmcntBitWidth()) - 1;
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}
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unsigned getExpcntBitMask(IsaVersion Version) {
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return (1 << getExpcntBitWidth()) - 1;
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}
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unsigned getLgkmcntBitMask(IsaVersion Version) {
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return (1 << getLgkmcntBitWidth()) - 1;
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}
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unsigned decodeVmcnt(IsaVersion Version, unsigned Waitcnt) {
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return unpackBits(Waitcnt, getVmcntBitShift(), getVmcntBitWidth());
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}
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unsigned decodeExpcnt(IsaVersion Version, unsigned Waitcnt) {
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return unpackBits(Waitcnt, getExpcntBitShift(), getExpcntBitWidth());
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}
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unsigned decodeLgkmcnt(IsaVersion Version, unsigned Waitcnt) {
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return unpackBits(Waitcnt, getLgkmcntBitShift(), getLgkmcntBitWidth());
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}
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void decodeWaitcnt(IsaVersion Version, unsigned Waitcnt,
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unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt) {
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Vmcnt = decodeVmcnt(Version, Waitcnt);
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Expcnt = decodeExpcnt(Version, Waitcnt);
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Lgkmcnt = decodeLgkmcnt(Version, Waitcnt);
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}
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unsigned encodeVmcnt(IsaVersion Version, unsigned Waitcnt, unsigned Vmcnt) {
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return packBits(Vmcnt, Waitcnt, getVmcntBitShift(), getVmcntBitWidth());
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}
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unsigned encodeExpcnt(IsaVersion Version, unsigned Waitcnt, unsigned Expcnt) {
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return packBits(Expcnt, Waitcnt, getExpcntBitShift(), getExpcntBitWidth());
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}
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unsigned encodeLgkmcnt(IsaVersion Version, unsigned Waitcnt, unsigned Lgkmcnt) {
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return packBits(Lgkmcnt, Waitcnt, getLgkmcntBitShift(), getLgkmcntBitWidth());
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}
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unsigned encodeWaitcnt(IsaVersion Version,
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unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt) {
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unsigned Waitcnt = getWaitcntBitMask(Version);;
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Waitcnt = encodeVmcnt(Version, Waitcnt, Vmcnt);
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Waitcnt = encodeExpcnt(Version, Waitcnt, Expcnt);
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Waitcnt = encodeLgkmcnt(Version, Waitcnt, Lgkmcnt);
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return Waitcnt;
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}
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unsigned getInitialPSInputAddr(const Function &F) {
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return getIntegerAttribute(F, "InitialPSInputAddr", 0);
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}
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bool isShader(CallingConv::ID cc) {
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switch(cc) {
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case CallingConv::AMDGPU_VS:
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case CallingConv::AMDGPU_GS:
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case CallingConv::AMDGPU_PS:
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case CallingConv::AMDGPU_CS:
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return true;
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default:
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return false;
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}
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}
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bool isCompute(CallingConv::ID cc) {
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return !isShader(cc) || cc == CallingConv::AMDGPU_CS;
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}
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bool isSI(const MCSubtargetInfo &STI) {
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return STI.getFeatureBits()[AMDGPU::FeatureSouthernIslands];
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}
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bool isCI(const MCSubtargetInfo &STI) {
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return STI.getFeatureBits()[AMDGPU::FeatureSeaIslands];
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}
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bool isVI(const MCSubtargetInfo &STI) {
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return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands];
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}
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unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI) {
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switch(Reg) {
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default: break;
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case AMDGPU::FLAT_SCR:
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assert(!isSI(STI));
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return isCI(STI) ? AMDGPU::FLAT_SCR_ci : AMDGPU::FLAT_SCR_vi;
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case AMDGPU::FLAT_SCR_LO:
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assert(!isSI(STI));
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return isCI(STI) ? AMDGPU::FLAT_SCR_LO_ci : AMDGPU::FLAT_SCR_LO_vi;
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case AMDGPU::FLAT_SCR_HI:
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assert(!isSI(STI));
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return isCI(STI) ? AMDGPU::FLAT_SCR_HI_ci : AMDGPU::FLAT_SCR_HI_vi;
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}
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return Reg;
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}
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bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo) {
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unsigned OpType = Desc.OpInfo[OpNo].OperandType;
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return OpType == AMDGPU::OPERAND_REG_IMM32_INT ||
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OpType == AMDGPU::OPERAND_REG_IMM32_FP ||
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OpType == AMDGPU::OPERAND_REG_INLINE_C_INT ||
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OpType == AMDGPU::OPERAND_REG_INLINE_C_FP;
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}
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bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo) {
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unsigned OpType = Desc.OpInfo[OpNo].OperandType;
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return OpType == AMDGPU::OPERAND_REG_IMM32_FP ||
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OpType == AMDGPU::OPERAND_REG_INLINE_C_FP;
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}
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bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo) {
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unsigned OpType = Desc.OpInfo[OpNo].OperandType;
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return OpType == AMDGPU::OPERAND_REG_INLINE_C_INT ||
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OpType == AMDGPU::OPERAND_REG_INLINE_C_FP;
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}
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// Avoid using MCRegisterClass::getSize, since that function will go away
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// (move from MC* level to Target* level). Return size in bits.
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unsigned getRegBitWidth(unsigned RCID) {
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switch (RCID) {
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case AMDGPU::SGPR_32RegClassID:
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case AMDGPU::VGPR_32RegClassID:
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case AMDGPU::VS_32RegClassID:
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case AMDGPU::SReg_32RegClassID:
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case AMDGPU::SReg_32_XM0RegClassID:
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return 32;
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case AMDGPU::SGPR_64RegClassID:
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case AMDGPU::VS_64RegClassID:
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case AMDGPU::SReg_64RegClassID:
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case AMDGPU::VReg_64RegClassID:
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return 64;
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case AMDGPU::VReg_96RegClassID:
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return 96;
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case AMDGPU::SGPR_128RegClassID:
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case AMDGPU::SReg_128RegClassID:
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case AMDGPU::VReg_128RegClassID:
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return 128;
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case AMDGPU::SReg_256RegClassID:
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case AMDGPU::VReg_256RegClassID:
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return 256;
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case AMDGPU::SReg_512RegClassID:
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case AMDGPU::VReg_512RegClassID:
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return 512;
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default:
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llvm_unreachable("Unexpected register class");
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}
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}
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unsigned getRegBitWidth(const MCRegisterClass &RC) {
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return getRegBitWidth(RC.getID());
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}
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unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc,
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unsigned OpNo) {
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unsigned RCID = Desc.OpInfo[OpNo].RegClass;
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return getRegBitWidth(MRI->getRegClass(RCID)) / 8;
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}
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bool isInlinableLiteral64(int64_t Literal, bool IsVI) {
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if (Literal >= -16 && Literal <= 64)
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return true;
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double D = BitsToDouble(Literal);
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if (D == 0.5 || D == -0.5 ||
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D == 1.0 || D == -1.0 ||
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D == 2.0 || D == -2.0 ||
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D == 4.0 || D == -4.0)
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return true;
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if (IsVI && Literal == 0x3fc45f306dc9c882)
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return true;
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return false;
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}
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bool isInlinableLiteral32(int32_t Literal, bool IsVI) {
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if (Literal >= -16 && Literal <= 64)
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return true;
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float F = BitsToFloat(Literal);
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if (F == 0.5 || F == -0.5 ||
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F == 1.0 || F == -1.0 ||
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F == 2.0 || F == -2.0 ||
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F == 4.0 || F == -4.0)
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return true;
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if (IsVI && Literal == 0x3e22f983)
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return true;
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return false;
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}
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} // End namespace AMDGPU
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} // End namespace llvm
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