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Instead, pattern match extends of extract_subvectors to generate widening operations. Since extract_subvector is not a legal node, this is implemented via a custom combine that recognizes extract_subvector nodes before they are legalized. The combine produces custom ISD nodes that are later pattern matched directly, just like the intrinsic was. Also removes the clang builtins for these operations since the instructions can now be generated from portable code sequences. Differential Revision: https://reviews.llvm.org/D84556
213 lines
8.8 KiB
TableGen
213 lines
8.8 KiB
TableGen
//===- IntrinsicsWebAssembly.td - Defines wasm intrinsics --*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// This file defines all of the WebAssembly-specific intrinsics.
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///
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//===----------------------------------------------------------------------===//
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let TargetPrefix = "wasm" in { // All intrinsics start with "llvm.wasm.".
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// Query the current memory size, and increase the current memory size.
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// Note that memory.size is not IntrNoMem because it must be sequenced with
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// respect to memory.grow calls.
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def int_wasm_memory_size : Intrinsic<[llvm_anyint_ty],
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[llvm_i32_ty],
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[IntrReadMem]>;
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def int_wasm_memory_grow : Intrinsic<[llvm_anyint_ty],
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[llvm_i32_ty, LLVMMatchType<0>],
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[]>;
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//===----------------------------------------------------------------------===//
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// Trapping float-to-int conversions
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//===----------------------------------------------------------------------===//
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def int_wasm_trunc_signed : Intrinsic<[llvm_anyint_ty],
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[llvm_anyfloat_ty],
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[IntrNoMem]>;
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def int_wasm_trunc_unsigned : Intrinsic<[llvm_anyint_ty],
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[llvm_anyfloat_ty],
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[IntrNoMem]>;
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//===----------------------------------------------------------------------===//
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// Saturating float-to-int conversions
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//===----------------------------------------------------------------------===//
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def int_wasm_trunc_saturate_signed : Intrinsic<[llvm_anyint_ty],
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[llvm_anyfloat_ty],
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[IntrNoMem, IntrSpeculatable]>;
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def int_wasm_trunc_saturate_unsigned : Intrinsic<[llvm_anyint_ty],
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[llvm_anyfloat_ty],
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[IntrNoMem, IntrSpeculatable]>;
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//===----------------------------------------------------------------------===//
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// Exception handling intrinsics
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//===----------------------------------------------------------------------===//
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// throw / rethrow
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def int_wasm_throw : Intrinsic<[], [llvm_i32_ty, llvm_ptr_ty],
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[Throws, IntrNoReturn, ImmArg<ArgIndex<0>>]>;
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def int_wasm_rethrow_in_catch : Intrinsic<[], [], [Throws, IntrNoReturn]>;
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// Since wasm does not use landingpad instructions, these instructions return
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// exception pointer and selector values until we lower them in WasmEHPrepare.
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def int_wasm_get_exception : Intrinsic<[llvm_ptr_ty], [llvm_token_ty],
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[IntrHasSideEffects]>;
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def int_wasm_get_ehselector : Intrinsic<[llvm_i32_ty], [llvm_token_ty],
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[IntrHasSideEffects]>;
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// This is the same as llvm.wasm.get.exception except that it does not take a
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// token operand. This is only for instruction selection purpose.
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def int_wasm_extract_exception : Intrinsic<[llvm_ptr_ty], [],
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[IntrHasSideEffects]>;
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// WebAssembly EH must maintain the landingpads in the order assigned to them
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// by WasmEHPrepare pass to generate landingpad table in EHStreamer. This is
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// used in order to give them the indices in WasmEHPrepare.
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def int_wasm_landingpad_index: Intrinsic<[], [llvm_token_ty, llvm_i32_ty],
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[IntrNoMem, ImmArg<ArgIndex<1>>]>;
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// Returns LSDA address of the current function.
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def int_wasm_lsda : Intrinsic<[llvm_ptr_ty], [], [IntrNoMem]>;
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//===----------------------------------------------------------------------===//
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// Atomic intrinsics
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//===----------------------------------------------------------------------===//
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// wait / notify
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def int_wasm_atomic_wait_i32 :
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Intrinsic<[llvm_i32_ty],
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[LLVMPointerType<llvm_i32_ty>, llvm_i32_ty, llvm_i64_ty],
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[IntrInaccessibleMemOrArgMemOnly, ReadOnly<ArgIndex<0>>, NoCapture<ArgIndex<0>>,
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IntrHasSideEffects],
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"", [SDNPMemOperand]>;
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def int_wasm_atomic_wait_i64 :
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Intrinsic<[llvm_i32_ty],
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[LLVMPointerType<llvm_i64_ty>, llvm_i64_ty, llvm_i64_ty],
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[IntrInaccessibleMemOrArgMemOnly, ReadOnly<ArgIndex<0>>, NoCapture<ArgIndex<0>>,
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IntrHasSideEffects],
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"", [SDNPMemOperand]>;
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def int_wasm_atomic_notify:
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Intrinsic<[llvm_i32_ty], [LLVMPointerType<llvm_i32_ty>, llvm_i32_ty],
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[IntrInaccessibleMemOnly, NoCapture<ArgIndex<0>>, IntrHasSideEffects], "",
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[SDNPMemOperand]>;
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//===----------------------------------------------------------------------===//
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// SIMD intrinsics
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//===----------------------------------------------------------------------===//
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def int_wasm_swizzle :
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Intrinsic<[llvm_v16i8_ty],
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[llvm_v16i8_ty, llvm_v16i8_ty],
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[IntrNoMem, IntrSpeculatable]>;
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def int_wasm_shuffle :
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Intrinsic<[llvm_v16i8_ty],
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[llvm_v16i8_ty, llvm_v16i8_ty, llvm_i32_ty, llvm_i32_ty,
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llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
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llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
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llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
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[IntrNoMem, IntrSpeculatable]>;
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def int_wasm_sub_saturate_signed :
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Intrinsic<[llvm_anyvector_ty],
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[LLVMMatchType<0>, LLVMMatchType<0>],
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[IntrNoMem, IntrSpeculatable]>;
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def int_wasm_sub_saturate_unsigned :
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Intrinsic<[llvm_anyvector_ty],
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[LLVMMatchType<0>, LLVMMatchType<0>],
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[IntrNoMem, IntrSpeculatable]>;
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def int_wasm_avgr_unsigned :
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Intrinsic<[llvm_anyvector_ty],
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[LLVMMatchType<0>, LLVMMatchType<0>],
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[IntrNoMem, IntrSpeculatable]>;
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def int_wasm_bitselect :
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Intrinsic<[llvm_anyvector_ty],
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[LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
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[IntrNoMem, IntrSpeculatable]>;
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def int_wasm_anytrue :
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Intrinsic<[llvm_i32_ty],
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[llvm_anyvector_ty],
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[IntrNoMem, IntrSpeculatable]>;
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def int_wasm_alltrue :
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Intrinsic<[llvm_i32_ty],
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[llvm_anyvector_ty],
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[IntrNoMem, IntrSpeculatable]>;
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def int_wasm_bitmask :
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Intrinsic<[llvm_i32_ty],
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[llvm_anyvector_ty],
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[IntrNoMem, IntrSpeculatable]>;
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def int_wasm_qfma :
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Intrinsic<[llvm_anyvector_ty],
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[LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
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[IntrNoMem, IntrSpeculatable]>;
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def int_wasm_qfms :
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Intrinsic<[llvm_anyvector_ty],
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[LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
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[IntrNoMem, IntrSpeculatable]>;
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def int_wasm_dot :
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Intrinsic<[llvm_v4i32_ty],
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[llvm_v8i16_ty, llvm_v8i16_ty],
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[IntrNoMem, IntrSpeculatable]>;
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def int_wasm_narrow_signed :
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Intrinsic<[llvm_anyvector_ty],
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[llvm_anyvector_ty, LLVMMatchType<1>],
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[IntrNoMem, IntrSpeculatable]>;
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def int_wasm_narrow_unsigned :
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Intrinsic<[llvm_anyvector_ty],
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[llvm_anyvector_ty, LLVMMatchType<1>],
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[IntrNoMem, IntrSpeculatable]>;
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// TODO: Replace these intrinsics with normal ISel patterns
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def int_wasm_pmin :
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Intrinsic<[llvm_anyvector_ty],
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[LLVMMatchType<0>, LLVMMatchType<0>],
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[IntrNoMem, IntrSpeculatable]>;
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def int_wasm_pmax :
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Intrinsic<[llvm_anyvector_ty],
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[LLVMMatchType<0>, LLVMMatchType<0>],
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[IntrNoMem, IntrSpeculatable]>;
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// TODO: Replace these instrinsics with normal ISel patterns once the
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// rounding instructions are merged to the proposal
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// (https://github.com/WebAssembly/simd/pull/232).
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def int_wasm_ceil :
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Intrinsic<[llvm_anyvector_ty],
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[LLVMMatchType<0>],
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[IntrNoMem, IntrSpeculatable]>;
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def int_wasm_floor :
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Intrinsic<[llvm_anyvector_ty],
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[LLVMMatchType<0>],
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[IntrNoMem, IntrSpeculatable]>;
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def int_wasm_trunc :
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Intrinsic<[llvm_anyvector_ty],
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[LLVMMatchType<0>],
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[IntrNoMem, IntrSpeculatable]>;
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def int_wasm_nearest :
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Intrinsic<[llvm_anyvector_ty],
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[LLVMMatchType<0>],
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[IntrNoMem, IntrSpeculatable]>;
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//===----------------------------------------------------------------------===//
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// Thread-local storage intrinsics
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//===----------------------------------------------------------------------===//
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def int_wasm_tls_size :
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Intrinsic<[llvm_anyint_ty],
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[],
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[IntrNoMem, IntrSpeculatable]>;
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def int_wasm_tls_align :
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Intrinsic<[llvm_anyint_ty],
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[],
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[IntrNoMem, IntrSpeculatable]>;
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def int_wasm_tls_base :
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Intrinsic<[llvm_ptr_ty],
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[],
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[IntrReadMem]>;
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} // TargetPrefix = "wasm"
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