Matt Arsenault c124c9a532 Revert "[amdgpu] Lower SGPR-to-VGPR copy in the final phase of ISel." ... This reverts commit c3492a1aa1b98c8d81b0969d52cea7681f0624c2. I think this is the wrong strategy and wrong place to do this transform anyway. Also reverts follow up commit 7d593d0d6905b55ca1124fca5e4d1ebb17203138.		2020-09-18 09:48:33 -04:00
..
Analysis	Recommit "[DSE] Switch to MemorySSA-backed DSE by default."	2020-09-18 11:05:00 +01:00
Assembler
Bindings
Bitcode
BugPoint
CodeGen	Revert "[amdgpu] Lower SGPR-to-VGPR copy in the final phase of ISel."	2020-09-18 09:48:33 -04:00
DebugInfo
Demangle
Examples
ExecutionEngine
Feature
FileCheck
Instrumentation
Integer
JitListener
Linker
LTO
MachineVerifier
MC	[PowerPC] Add Set Boolean Condition Instruction Definitions and MC Tests	2020-09-17 18:20:54 -05:00
Object
ObjectYAML	[DWARFYAML] Make the include_directories, file_names and opcodes fields of the line table optional.	2020-09-18 20:21:11 +08:00
Other	Recommit "[DSE] Switch to MemorySSA-backed DSE by default."	2020-09-18 11:05:00 +01:00
Reduce
SafepointIRVerifier
Support
SymbolRewriter
TableGen	[TableGen][GlobalISel] Fix handling of zero_reg	2020-09-18 11:01:11 +02:00
ThinLTO/X86
tools	[DWARFYAML] Make the include_directories, file_names and opcodes fields of the line table optional.	2020-09-18 20:21:11 +08:00
Transforms	[SLP] Allow reordering of vectorization trees with reused instructions.	2020-09-18 09:34:59 -04:00
Unit
Verifier
YAMLParser
.clang-format
CMakeLists.txt
lit.cfg.py
lit.site.cfg.py.in
TestRunner.sh