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78 lines
3.1 KiB
TableGen
78 lines
3.1 KiB
TableGen
//====- X86Instr3DNow.td - The 3DNow! Instruction Set ------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the 3DNow! instruction set, which extends MMX to support
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// floating point and also adds a few more random instructions for good measure.
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//
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//===----------------------------------------------------------------------===//
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// FIXME: We don't support any intrinsics for these instructions yet.
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class I3DNow<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern>
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: I<o, F, outs, ins, asm, pattern>, TB, Requires<[Has3DNow]> {
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}
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class I3DNow_binop<bits<8> o, Format F, dag ins, string Mnemonic>
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: I<o, F, (outs VR64:$dst), ins,
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!strconcat(Mnemonic, "\t{$src2, $dst|$dst, $src2}"), []>,
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TB, Requires<[Has3DNow]>, Has3DNow0F0FOpcode {
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// FIXME: The disassembler doesn't support Has3DNow0F0FOpcode yet.
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let isAsmParserOnly = 1;
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}
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let Constraints = "$src1 = $dst" in {
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// MMXI_binop_rm_int - Simple MMX binary operator based on intrinsic.
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// When this is cleaned up, remove the FIXME from X86RecognizableInstr.cpp.
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multiclass I3DNow_binop_rm<bits<8> opc, string Mn> {
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def rr : I3DNow_binop<opc, MRMSrcReg, (ins VR64:$src1, VR64:$src2), Mn>;
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def rm : I3DNow_binop<opc, MRMSrcMem, (ins VR64:$src1, i64mem:$src2), Mn>;
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}
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}
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defm PAVGUSB : I3DNow_binop_rm<0xBF, "pavgusb">;
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defm PF2ID : I3DNow_binop_rm<0x1D, "pf2id">;
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defm PFACC : I3DNow_binop_rm<0xAE, "pfacc">;
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defm PFADD : I3DNow_binop_rm<0x9E, "pfadd">;
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defm PFCMPEQ : I3DNow_binop_rm<0xB0, "pfcmpeq">;
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defm PFCMPGE : I3DNow_binop_rm<0x90, "pfcmpge">;
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defm PFCMPGT : I3DNow_binop_rm<0xA0, "pfcmpgt">;
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defm PFMAX : I3DNow_binop_rm<0xA4, "pfmax">;
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defm PFMIN : I3DNow_binop_rm<0x94, "pfmin">;
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defm PFMUL : I3DNow_binop_rm<0xB4, "pfmul">;
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defm PFRCP : I3DNow_binop_rm<0x96, "pfrcp">;
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defm PFRCPIT1 : I3DNow_binop_rm<0xA6, "pfrcpit1">;
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defm PFRCPIT2 : I3DNow_binop_rm<0xB6, "pfrcpit2">;
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defm PFRSQIT1 : I3DNow_binop_rm<0xA7, "pfrsqit1">;
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defm PFRSQRT : I3DNow_binop_rm<0x97, "pfrsqrt">;
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defm PFSUB : I3DNow_binop_rm<0x9A, "pfsub">;
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defm PFSUBR : I3DNow_binop_rm<0xAA, "pfsubr">;
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defm PI2FD : I3DNow_binop_rm<0x0D, "pi2fd">;
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defm PMULHRW : I3DNow_binop_rm<0xB7, "pmulhrw">;
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def FEMMS : I3DNow<0x0E, RawFrm, (outs), (ins), "femms", [(int_x86_mmx_femms)]>;
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def PREFETCH : I3DNow<0x0D, MRM0m, (outs), (ins i32mem:$addr),
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"prefetch $addr", []>;
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// FIXME: Diassembler gets a bogus decode conflict.
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let isAsmParserOnly = 1 in {
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def PREFETCHW : I3DNow<0x0D, MRM1m, (outs), (ins i16mem:$addr),
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"prefetchw $addr", []>;
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}
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// "3DNowA" instructions
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defm PF2IW : I3DNow_binop_rm<0x1C, "pf2iw">;
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defm PI2FW : I3DNow_binop_rm<0x0C, "pi2fw">;
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defm PFNACC : I3DNow_binop_rm<0x8A, "pfnacc">;
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defm PFPNACC : I3DNow_binop_rm<0x8E, "pfpnacc">;
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defm PSWAPD : I3DNow_binop_rm<0xBB, "pswapd">;
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