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to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
640 lines
16 KiB
TableGen
640 lines
16 KiB
TableGen
//===- Mips16InstrFormats.td - Mips Instruction Formats ----*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Describe MIPS instructions format
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//
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// CPU INSTRUCTION FORMATS
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//
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// funct or f Function field
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//
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// immediate 4-,5-,8- or 11-bit immediate, branch displacement, or
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// or imm address displacement
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//
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// op 5-bit major operation code
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//
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// rx 3-bit source or destination register
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//
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// ry 3-bit source or destination register
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//
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// rz 3-bit source or destination register
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//
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// sa 3- or 5-bit shift amount
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//
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//===----------------------------------------------------------------------===//
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// Base class for Mips 16 Format
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// This class does not depend on the instruction size
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//
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class MipsInst16_Base<dag outs, dag ins, string asmstr, list<dag> pattern,
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InstrItinClass itin>: Instruction
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{
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let Namespace = "Mips";
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let OutOperandList = outs;
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let InOperandList = ins;
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let AsmString = asmstr;
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let Pattern = pattern;
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let Itinerary = itin;
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let Predicates = [InMips16Mode];
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}
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//
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// Generic Mips 16 Format
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//
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class MipsInst16<dag outs, dag ins, string asmstr, list<dag> pattern,
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InstrItinClass itin>:
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MipsInst16_Base<outs, ins, asmstr, pattern, itin>
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{
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field bits<16> Inst;
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bits<5> Opcode = 0;
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// Top 5 bits are the 'opcode' field
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let Inst{15-11} = Opcode;
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let Size=2;
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field bits<16> SoftFail = 0;
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}
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//
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// For 32 bit extended instruction forms.
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//
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class MipsInst16_32<dag outs, dag ins, string asmstr, list<dag> pattern,
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InstrItinClass itin>:
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MipsInst16_Base<outs, ins, asmstr, pattern, itin>
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{
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field bits<32> Inst;
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let Size=4;
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field bits<32> SoftFail = 0;
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}
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class MipsInst16_EXTEND<dag outs, dag ins, string asmstr, list<dag> pattern,
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InstrItinClass itin>:
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MipsInst16_32<outs, ins, asmstr, pattern, itin>
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{
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let Inst{31-27} = 0b11110;
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}
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// Mips Pseudo Instructions Format
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class MipsPseudo16<dag outs, dag ins, string asmstr, list<dag> pattern>:
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MipsInst16<outs, ins, asmstr, pattern, IIPseudo> {
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let isCodeGenOnly = 1;
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let isPseudo = 1;
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}
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//===----------------------------------------------------------------------===//
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// Format I instruction class in Mips : <|opcode|imm11|>
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//===----------------------------------------------------------------------===//
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class FI16<bits<5> op, dag outs, dag ins, string asmstr, list<dag> pattern,
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InstrItinClass itin>:
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MipsInst16<outs, ins, asmstr, pattern, itin>
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{
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bits<11> imm11;
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let Opcode = op;
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let Inst{10-0} = imm11;
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}
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//===----------------------------------------------------------------------===//
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// Format RI instruction class in Mips : <|opcode|rx|imm8|>
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//===----------------------------------------------------------------------===//
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class FRI16<bits<5> op, dag outs, dag ins, string asmstr,
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list<dag> pattern, InstrItinClass itin>:
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MipsInst16<outs, ins, asmstr, pattern, itin>
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{
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bits<3> rx;
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bits<8> imm8;
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let Opcode = op;
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let Inst{10-8} = rx;
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let Inst{7-0} = imm8;
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}
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//===----------------------------------------------------------------------===//
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// Format RR instruction class in Mips : <|opcode|rx|ry|funct|>
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//===----------------------------------------------------------------------===//
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class FRR16<bits<5> _funct, dag outs, dag ins, string asmstr,
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list<dag> pattern, InstrItinClass itin>:
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MipsInst16<outs, ins, asmstr, pattern, itin>
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{
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bits<3> rx;
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bits<3> ry;
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bits<5> funct;
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let Opcode = 0b11101;
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let funct = _funct;
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let Inst{10-8} = rx;
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let Inst{7-5} = ry;
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let Inst{4-0} = funct;
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}
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class FRRBreak16<dag outs, dag ins, string asmstr,
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list<dag> pattern, InstrItinClass itin>:
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MipsInst16<outs, ins, asmstr, pattern, itin>
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{
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bits<6> Code;
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bits<5> funct;
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let Opcode = 0b11101;
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let funct = 0b00101;
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let Inst{10-5} = Code;
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let Inst{4-0} = funct;
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}
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//
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// For conversion functions.
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//
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class FRR_SF16<bits<5> _funct, bits<3> _subfunct, dag outs, dag ins,
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string asmstr, list<dag> pattern, InstrItinClass itin>:
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MipsInst16<outs, ins, asmstr, pattern, itin>
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{
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bits<3> rx;
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bits<3> subfunct;
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bits<5> funct;
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let Opcode = 0b11101; // RR
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let funct = _funct;
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let subfunct = _subfunct;
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let Inst{10-8} = rx;
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let Inst{7-5} = subfunct;
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let Inst{4-0} = funct;
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}
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//
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// just used for breakpoint (hardware and software) instructions.
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//
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class FC16<bits<5> _funct, dag outs, dag ins, string asmstr,
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list<dag> pattern, InstrItinClass itin>:
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MipsInst16<outs, ins, asmstr, pattern, itin>
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{
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bits<6> _code; // code is a keyword in tablegen
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bits<5> funct;
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let Opcode = 0b11101; // RR
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let funct = _funct;
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let Inst{10-5} = _code;
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let Inst{4-0} = funct;
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}
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//
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// J(AL)R(C) subformat
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//
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class FRR16_JALRC<bits<1> _nd, bits<1> _l, bits<1> r_a,
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dag outs, dag ins, string asmstr,
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list<dag> pattern, InstrItinClass itin>:
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MipsInst16<outs, ins, asmstr, pattern, itin>
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{
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bits<3> rx;
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bits<1> nd;
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bits<1> l;
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bits<1> ra;
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let nd = _nd;
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let l = _l;
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let ra = r_a;
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let Opcode = 0b11101;
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let Inst{10-8} = rx;
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let Inst{7} = nd;
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let Inst{6} = l;
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let Inst{5} = ra;
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let Inst{4-0} = 0;
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}
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//===----------------------------------------------------------------------===//
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// Format RRI instruction class in Mips : <|opcode|rx|ry|imm5|>
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//===----------------------------------------------------------------------===//
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class FRRI16<bits<5> op, dag outs, dag ins, string asmstr,
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list<dag> pattern, InstrItinClass itin>:
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MipsInst16<outs, ins, asmstr, pattern, itin>
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{
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bits<3> rx;
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bits<3> ry;
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bits<5> imm5;
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let Opcode = op;
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let Inst{10-8} = rx;
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let Inst{7-5} = ry;
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let Inst{4-0} = imm5;
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}
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//===----------------------------------------------------------------------===//
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// Format RRR instruction class in Mips : <|opcode|rx|ry|rz|f|>
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//===----------------------------------------------------------------------===//
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class FRRR16<bits<2> _f, dag outs, dag ins, string asmstr,
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list<dag> pattern, InstrItinClass itin>:
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MipsInst16<outs, ins, asmstr, pattern, itin>
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{
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bits<3> rx;
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bits<3> ry;
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bits<3> rz;
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bits<2> f;
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let Opcode = 0b11100;
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let f = _f;
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let Inst{10-8} = rx;
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let Inst{7-5} = ry;
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let Inst{4-2} = rz;
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let Inst{1-0} = f;
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}
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//===----------------------------------------------------------------------===//
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// Format RRI-A instruction class in Mips : <|opcode|rx|ry|f|imm4|>
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//===----------------------------------------------------------------------===//
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class FRRI_A16<bits<1> _f, dag outs, dag ins, string asmstr,
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list<dag> pattern, InstrItinClass itin>:
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MipsInst16<outs, ins, asmstr, pattern, itin>
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{
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bits<3> rx;
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bits<3> ry;
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bits<1> f;
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bits<4> imm4;
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let Opcode = 0b01000;
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let f = _f;
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let Inst{10-8} = rx;
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let Inst{7-5} = ry;
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let Inst{4} = f;
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let Inst{3-0} = imm4;
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}
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//===----------------------------------------------------------------------===//
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// Format Shift instruction class in Mips : <|opcode|rx|ry|sa|f|>
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//===----------------------------------------------------------------------===//
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class FSHIFT16<bits<2> _f, dag outs, dag ins, string asmstr,
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list<dag> pattern, InstrItinClass itin>:
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MipsInst16<outs, ins, asmstr, pattern, itin>
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{
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bits<3> rx;
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bits<3> ry;
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bits<3> sa;
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bits<2> f;
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let Opcode = 0b00110;
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let f = _f;
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let Inst{10-8} = rx;
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let Inst{7-5} = ry;
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let Inst{4-2} = sa;
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let Inst{1-0} = f;
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}
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//===----------------------------------------------------------------------===//
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// Format i8 instruction class in Mips : <|opcode|funct|imm8>
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//===----------------------------------------------------------------------===//
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class FI816<bits<3> _func, dag outs, dag ins, string asmstr,
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list<dag> pattern, InstrItinClass itin>:
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MipsInst16<outs, ins, asmstr, pattern, itin>
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{
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bits<3> func;
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bits<8> imm8;
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let Opcode = 0b01100;
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let func = _func;
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let Inst{10-8} = func;
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let Inst{7-0} = imm8;
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}
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//===----------------------------------------------------------------------===//
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// Format i8_MOVR32 instruction class in Mips : <|opcode|func|ry|r32>
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//===----------------------------------------------------------------------===//
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class FI8_MOVR3216<dag outs, dag ins, string asmstr,
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list<dag> pattern, InstrItinClass itin>:
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MipsInst16<outs, ins, asmstr, pattern, itin>
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{
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bits<4> ry;
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bits<4> r32;
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let Opcode = 0b01100;
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let Inst{10-8} = 0b111;
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let Inst{7-4} = ry;
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let Inst{3-0} = r32;
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}
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//===----------------------------------------------------------------------===//
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// Format i8_MOV32R instruction class in Mips : <|opcode|func|r32|rz>
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//===----------------------------------------------------------------------===//
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class FI8_MOV32R16<dag outs, dag ins, string asmstr,
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list<dag> pattern, InstrItinClass itin>:
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MipsInst16<outs, ins, asmstr, pattern, itin>
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{
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bits<3> func;
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bits<5> r32;
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bits<3> rz;
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let Opcode = 0b01100;
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let Inst{10-8} = 0b101;
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let Inst{7-5} = r32{2-0};
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let Inst{4-3} = r32{4-3};
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let Inst{2-0} = rz;
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}
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//===----------------------------------------------------------------------===//
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// Format i8_SVRS instruction class in Mips :
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// <|opcode|svrs|s|ra|s0|s1|framesize>
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//===----------------------------------------------------------------------===//
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class FI8_SVRS16<bits<1> _s, dag outs, dag ins, string asmstr,
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list<dag> pattern, InstrItinClass itin>:
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MipsInst16<outs, ins, asmstr, pattern, itin>
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{
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bits<1> s;
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bits<1> ra = 0;
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bits<1> s0 = 0;
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bits<1> s1 = 0;
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bits<4> framesize = 0;
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let s =_s;
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let Opcode = 0b01100;
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let Inst{10-8} = 0b100;
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let Inst{7} = s;
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let Inst{6} = ra;
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let Inst{5} = s0;
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let Inst{4} = s1;
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let Inst{3-0} = framesize;
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}
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//===----------------------------------------------------------------------===//
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// Format JAL instruction class in Mips16 :
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// <|opcode|svrs|s|ra|s0|s1|framesize>
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//===----------------------------------------------------------------------===//
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class FJAL16<bits<1> _X, dag outs, dag ins, string asmstr,
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list<dag> pattern, InstrItinClass itin>:
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MipsInst16_32<outs, ins, asmstr, pattern, itin>
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{
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bits<1> X;
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bits<26> imm26;
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let X = _X;
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let Inst{31-27} = 0b00011;
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let Inst{26} = X;
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let Inst{25-21} = imm26{20-16};
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let Inst{20-16} = imm26{25-21};
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let Inst{15-0} = imm26{15-0};
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}
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//===----------------------------------------------------------------------===//
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// Format EXT-I instruction class in Mips16 :
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// <|EXTEND|imm10:5|imm15:11|op|0|0|0|0|0|0|imm4:0>
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//===----------------------------------------------------------------------===//
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class FEXT_I16<bits<5> _eop, dag outs, dag ins, string asmstr,
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list<dag> pattern, InstrItinClass itin>:
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MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin>
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{
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bits<16> imm16;
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bits<5> eop;
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let eop = _eop;
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let Inst{26-21} = imm16{10-5};
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let Inst{20-16} = imm16{15-11};
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let Inst{15-11} = eop;
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let Inst{10-5} = 0;
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let Inst{4-0} = imm16{4-0};
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}
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//===----------------------------------------------------------------------===//
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// Format ASMACRO instruction class in Mips16 :
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// <EXTEND|select|p4|p3|RRR|p2|p1|p0>
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//===----------------------------------------------------------------------===//
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class FASMACRO16<dag outs, dag ins, string asmstr,
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list<dag> pattern, InstrItinClass itin>:
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MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin>
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{
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bits<3> select;
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bits<3> p4;
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bits<5> p3;
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bits<5> RRR = 0b11100;
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bits<3> p2;
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bits<3> p1;
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bits<5> p0;
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let Inst{26-24} = select;
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let Inst{23-21} = p4;
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let Inst{20-16} = p3;
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let Inst{15-11} = RRR;
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let Inst{10-8} = p2;
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let Inst{7-5} = p1;
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let Inst{4-0} = p0;
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}
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//===----------------------------------------------------------------------===//
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// Format EXT-RI instruction class in Mips16 :
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// <|EXTEND|imm10:5|imm15:11|op|rx|0|0|0|imm4:0>
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//===----------------------------------------------------------------------===//
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class FEXT_RI16<bits<5> _op, dag outs, dag ins, string asmstr,
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list<dag> pattern, InstrItinClass itin>:
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MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin>
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{
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bits<16> imm16;
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bits<5> op;
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bits<3> rx;
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let op = _op;
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let Inst{26-21} = imm16{10-5};
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let Inst{20-16} = imm16{15-11};
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let Inst{15-11} = op;
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let Inst{10-8} = rx;
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let Inst{7-5} = 0;
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let Inst{4-0} = imm16{4-0};
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}
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//===----------------------------------------------------------------------===//
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// Format EXT-RRI instruction class in Mips16 :
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// <|EXTEND|imm10:5|imm15:11|op|rx|ry|imm4:0>
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//===----------------------------------------------------------------------===//
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class FEXT_RRI16<bits<5> _op, dag outs, dag ins, string asmstr,
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list<dag> pattern, InstrItinClass itin>:
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MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin>
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{
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bits<5> op;
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bits<16> imm16;
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bits<3> rx;
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bits<3> ry;
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let op=_op;
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let Inst{26-21} = imm16{10-5};
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let Inst{20-16} = imm16{15-11};
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let Inst{15-11} = op;
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let Inst{10-8} = rx;
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let Inst{7-5} = ry;
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let Inst{4-0} = imm16{4-0};
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}
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//===----------------------------------------------------------------------===//
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// Format EXT-RRI-A instruction class in Mips16 :
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// <|EXTEND|imm10:4|imm14:11|RRI-A|rx|ry|f|imm3:0>
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//===----------------------------------------------------------------------===//
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class FEXT_RRI_A16<bits<1> _f, dag outs, dag ins, string asmstr,
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list<dag> pattern, InstrItinClass itin>:
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MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin>
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|
{
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|
bits<15> imm15;
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|
bits<3> rx;
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|
bits<3> ry;
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|
bits<1> f;
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|
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let f = _f;
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|
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let Inst{26-20} = imm15{10-4};
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|
let Inst{19-16} = imm15{14-11};
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|
let Inst{15-11} = 0b01000;
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|
let Inst{10-8} = rx;
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|
let Inst{7-5} = ry;
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|
let Inst{4} = f;
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|
let Inst{3-0} = imm15{3-0};
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|
|
|
}
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|
|
|
//===----------------------------------------------------------------------===//
|
|
// Format EXT-SHIFT instruction class in Mips16 :
|
|
// <|EXTEND|sa 4:0|s5|0|SHIFT|rx|ry|0|f>
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
class FEXT_SHIFT16<bits<2> _f, dag outs, dag ins, string asmstr,
|
|
list<dag> pattern, InstrItinClass itin>:
|
|
MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin>
|
|
{
|
|
bits<6> sa6;
|
|
bits<3> rx;
|
|
bits<3> ry;
|
|
bits<2> f;
|
|
|
|
let f = _f;
|
|
|
|
let Inst{26-22} = sa6{4-0};
|
|
let Inst{21} = sa6{5};
|
|
let Inst{20-16} = 0;
|
|
let Inst{15-11} = 0b00110;
|
|
let Inst{10-8} = rx;
|
|
let Inst{7-5} = ry;
|
|
let Inst{4-2} = 0;
|
|
let Inst{1-0} = f;
|
|
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Format EXT-I8 instruction class in Mips16 :
|
|
// <|EXTEND|imm10:5|imm15:11|I8|funct|0|imm4:0>
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
class FEXT_I816<bits<3> _funct, dag outs, dag ins, string asmstr,
|
|
list<dag> pattern, InstrItinClass itin>:
|
|
MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin>
|
|
{
|
|
bits<16> imm16;
|
|
bits<5> I8;
|
|
bits<3> funct;
|
|
|
|
let funct = _funct;
|
|
let I8 = 0b00110;
|
|
|
|
let Inst{26-21} = imm16{10-5};
|
|
let Inst{20-16} = imm16{15-11};
|
|
let Inst{15-11} = I8;
|
|
let Inst{10-8} = funct;
|
|
let Inst{7-5} = 0;
|
|
let Inst{4-0} = imm16{4-0};
|
|
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Format EXT-I8_SVRS instruction class in Mips16 :
|
|
// <|EXTEND|xsregs|framesize7:4|aregs|I8|SVRS|s|ra|s0|s1|framesize3:0>
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
class FEXT_I8_SVRS16<bits<1> s_, dag outs, dag ins, string asmstr,
|
|
list<dag> pattern, InstrItinClass itin>:
|
|
MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin>
|
|
{
|
|
bits<3> xsregs =0;
|
|
bits<8> framesize =0;
|
|
bits<3> aregs =0;
|
|
bits<5> I8 = 0b01100;
|
|
bits<3> SVRS = 0b100;
|
|
bits<1> s;
|
|
bits<1> ra = 0;
|
|
bits<1> s0 = 0;
|
|
bits<1> s1 = 0;
|
|
|
|
let s= s_;
|
|
|
|
let Inst{26-24} = xsregs;
|
|
let Inst{23-20} = framesize{7-4};
|
|
let Inst{19} = 0;
|
|
let Inst{18-16} = aregs;
|
|
let Inst{15-11} = I8;
|
|
let Inst{10-8} = SVRS;
|
|
let Inst{7} = s;
|
|
let Inst{6} = ra;
|
|
let Inst{5} = s0;
|
|
let Inst{4} = s1;
|
|
let Inst{3-0} = framesize{3-0};
|
|
|
|
|
|
}
|
|
|