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mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-20 19:42:54 +02:00
llvm-mirror/test/CodeGen
Alexei Starovoitov 8cc8aba19c [bpf] add big- and host- endian support
Summary:
-march=bpf    -> host endian
-march=bpf_le -> little endian
-match=bpf_be -> big endian

Test Plan:
v1 was tested by IBM s390 guys and appears to be working there.
It bit rots too fast here.

Reviewers: chandlerc, tstellarAMD

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10177

llvm-svn: 239071
2015-06-04 19:15:05 +00:00
..
AArch64 Don't create a MIN/MAX node if the underlying compare has more than one use. 2015-06-04 13:48:23 +00:00
ARM ARM: Thumb2 LDRD/STRD supports independent input/output regs 2015-06-03 16:30:24 +00:00
BPF [bpf] add big- and host- endian support 2015-06-04 19:15:05 +00:00
CPP [opaque pointer type] Add textual IR support for explicit type parameter to the call instruction 2015-04-16 23:24:18 +00:00
Generic Resubmit r237954 (MIR Serialization: print and parse LLVM IR using MIR format). 2015-05-27 18:02:19 +00:00
Hexagon [Hexagon] Test doesn't work on all platforms. At any rate the uninitialized variable issue was fixed. Removing re-registering ASM backend. 2015-06-03 18:00:45 +00:00
Inputs IR: Give 'DI' prefix to debug info metadata 2015-04-29 16:38:44 +00:00
Mips [mips] Make TTypeEncoding indirect to allow .eh_frame to be read-only. 2015-06-02 20:32:50 +00:00
MIR MIR Serialization: use correct line and column numbers for LLVM IR errors. 2015-05-29 17:05:41 +00:00
MSP430 [opaque pointer type] Add textual IR support for explicit type parameter to gep operator 2015-03-13 18:20:45 +00:00
NVPTX [NVPTXFavorNonGenericAddrSpaces] recursively trace into GEP and BitCast 2015-05-29 17:00:27 +00:00
PowerPC Add support for VSX FMA single-precision instructions to the PPC back end 2015-05-29 17:13:25 +00:00
R600 R600/SI: Reimplement isLegalAddressingMode 2015-06-04 16:17:42 +00:00
SPARC Add support for the Sparc implementation-defined "ASR" registers. 2015-05-18 16:29:48 +00:00
SystemZ [DAGCombiner] Account for getVectorIdxTy() when narrowing vector load 2015-05-05 19:34:10 +00:00
Thumb Thumb2: Modify codegen for memcpy intrinsic to prefer LDM/STM. 2015-05-28 20:02:45 +00:00
Thumb2 ARM: Thumb2 LDRD/STRD supports independent input/output regs 2015-06-03 16:30:24 +00:00
WinEH [WinEH] C++ EH state numbering fixes 2015-05-20 23:22:24 +00:00
X86 [DAGCombiner] Fix wrong folding of a build_vector into a blend with zero. 2015-06-04 19:15:01 +00:00
XCore IR: Give 'DI' prefix to debug info metadata 2015-04-29 16:38:44 +00:00