David Sherwood cee8b18db2 [CodeGen] Canonicalise adds/subs of i1 vectors using XOR ... When calling SelectionDAG::getNode() to create an ADD or SUB of two vectors with i1 element types we can canonicalise this to use XOR instead, where 1+1 is treated as wrapping around to 0 and 0-1 wraps to 1. I've added the following tests for SVE targets: CodeGen/AArch64/sve-pred-arith.ll and modified some X86 tests to reflect the much simpler codegen required. Differential Revision: https://reviews.llvm.org/D97276		2021-02-25 10:31:26 +00:00
..
Analysis	[AArch64] Add abs intrinsic costs	2021-02-25 09:31:52 +00:00
Assembler
Bindings
Bitcode	Add auto-upgrade support for annotation intrinsics	2021-02-22 15:42:16 -08:00
BugPoint
CodeGen	[CodeGen] Canonicalise adds/subs of i1 vectors using XOR	2021-02-25 10:31:26 +00:00
DebugInfo	[CodeGen] Fix two dots between text section name and symbol name	2021-02-20 10:15:48 +08:00
Demangle
Examples	Revert "patch" it wass my mistake inusing git	2021-02-24 11:06:16 +05:30
ExecutionEngine
Feature
FileCheck
Instrumentation	[test] Improve SanitizerCoverage tests on !associated and comdat	2021-02-24 16:51:41 -08:00
Integer
JitListener
Linker	[llvm-link] fix IRMover returning wrong modified vector type	2021-02-22 11:29:42 +00:00
LTO
MachineVerifier
MC	[MC][ARM] make Thumb function also if type attribute is set	2021-02-24 14:08:56 -08:00
Object
ObjectYAML
Other	[ThinLTO][NewPM] Clean up dead code under -O0	2021-02-24 17:08:57 -08:00
Reduce
SafepointIRVerifier
Support
SymbolRewriter
TableGen
ThinLTO/X86	[WPD] Fix handling of pure virtual base class	2021-02-23 16:07:09 -08:00
tools	[llvm-objcopy] If input=output, preserve umask bits, otherwise drop S_ISUID/S_ISGID bits	2021-02-24 11:10:09 -08:00
Transforms	[NARY][NFC] New tests for upcoming changes.	2021-02-25 10:52:35 +07:00
Unit
Verifier	[IR] restrict vector reduction intrinsic types	2021-02-21 12:37:00 -05:00
YAMLParser
.clang-format
CMakeLists.txt
lit.cfg.py
lit.site.cfg.py.in
TestRunner.sh