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https://github.com/RPCS3/llvm-mirror.git
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ca0f4dc4f0
This commit starts with a "git mv ARM64 AArch64" and continues out from there, renaming the C++ classes, intrinsics, and other target-local objects for consistency. "ARM64" test directories are also moved, and tests that began their life in ARM64 use an arm64 triple, those from AArch64 use an aarch64 triple. Both should be equivalent though. This finishes the AArch64 merge, and everyone should feel free to continue committing as normal now. llvm-svn: 209577
68 lines
1.5 KiB
LLVM
68 lines
1.5 KiB
LLVM
; RUN: llc < %s -march=arm64 | FileCheck %s
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define i64 @_f0(i64* %p) {
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; CHECK: f0:
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; CHECK: ldur x0, [x0, #-8]
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; CHECK-NEXT: ret
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%tmp = getelementptr inbounds i64* %p, i64 -1
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%ret = load i64* %tmp, align 2
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ret i64 %ret
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}
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define i32 @_f1(i32* %p) {
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; CHECK: f1:
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; CHECK: ldur w0, [x0, #-4]
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; CHECK-NEXT: ret
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%tmp = getelementptr inbounds i32* %p, i64 -1
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%ret = load i32* %tmp, align 2
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ret i32 %ret
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}
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define i16 @_f2(i16* %p) {
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; CHECK: f2:
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; CHECK: ldurh w0, [x0, #-2]
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; CHECK-NEXT: ret
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%tmp = getelementptr inbounds i16* %p, i64 -1
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%ret = load i16* %tmp, align 2
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ret i16 %ret
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}
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define i8 @_f3(i8* %p) {
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; CHECK: f3:
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; CHECK: ldurb w0, [x0, #-1]
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; CHECK-NEXT: ret
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%tmp = getelementptr inbounds i8* %p, i64 -1
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%ret = load i8* %tmp, align 2
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ret i8 %ret
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}
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define i64 @zext32(i8* %a) nounwind ssp {
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; CHECK-LABEL: zext32:
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; CHECK: ldur w0, [x0, #-12]
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; CHECK-NEXT: ret
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%p = getelementptr inbounds i8* %a, i64 -12
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%tmp1 = bitcast i8* %p to i32*
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%tmp2 = load i32* %tmp1, align 4
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%ret = zext i32 %tmp2 to i64
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ret i64 %ret
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}
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define i64 @zext16(i8* %a) nounwind ssp {
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; CHECK-LABEL: zext16:
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; CHECK: ldurh w0, [x0, #-12]
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; CHECK-NEXT: ret
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%p = getelementptr inbounds i8* %a, i64 -12
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%tmp1 = bitcast i8* %p to i16*
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%tmp2 = load i16* %tmp1, align 2
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%ret = zext i16 %tmp2 to i64
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ret i64 %ret
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}
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define i64 @zext8(i8* %a) nounwind ssp {
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; CHECK-LABEL: zext8:
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; CHECK: ldurb w0, [x0, #-12]
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; CHECK-NEXT: ret
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%p = getelementptr inbounds i8* %a, i64 -12
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%tmp2 = load i8* %p, align 1
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%ret = zext i8 %tmp2 to i64
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ret i64 %ret
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}
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