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7155e98904
flags. They are still not enable in this revision. Added TargetInstrInfo::isZeroCost() to fix a fundamental problem with the scheduler's model of operand latency in the selection DAG. Generalized unit tests to work with sched-cycles. llvm-svn: 123969
54 lines
1.5 KiB
LLVM
54 lines
1.5 KiB
LLVM
; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2
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; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NFP0
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; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=CORTEXA8
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; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=CORTEXA9
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define float @test1(float* %a) {
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entry:
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%0 = load float* %a, align 4 ; <float> [#uses=2]
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%1 = fsub float -0.000000e+00, %0 ; <float> [#uses=2]
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%2 = fpext float %1 to double ; <double> [#uses=1]
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%3 = fcmp olt double %2, 1.234000e+00 ; <i1> [#uses=1]
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%retval = select i1 %3, float %1, float %0 ; <float> [#uses=1]
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ret float %retval
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}
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; VFP2: test1:
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; VFP2: vneg.f32 s{{.*}}, s{{.*}}
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; NFP1: test1:
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; NFP1: vneg.f32 d{{.*}}, d{{.*}}
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; NFP0: test1:
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; NFP0: vneg.f32 s{{.*}}, s{{.*}}
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; CORTEXA8: test1:
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; CORTEXA8: vneg.f32 d{{.*}}, d{{.*}}
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; CORTEXA9: test1:
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; CORTEXA9: vneg.f32 s{{.*}}, s{{.*}}
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define float @test2(float* %a) {
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entry:
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%0 = load float* %a, align 4 ; <float> [#uses=2]
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%1 = fmul float -1.000000e+00, %0 ; <float> [#uses=2]
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%2 = fpext float %1 to double ; <double> [#uses=1]
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%3 = fcmp olt double %2, 1.234000e+00 ; <i1> [#uses=1]
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%retval = select i1 %3, float %1, float %0 ; <float> [#uses=1]
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ret float %retval
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}
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; VFP2: test2:
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; VFP2: vneg.f32 s{{.*}}, s{{.*}}
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; NFP1: test2:
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; NFP1: vneg.f32 d{{.*}}, d{{.*}}
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; NFP0: test2:
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; NFP0: vneg.f32 s{{.*}}, s{{.*}}
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; CORTEXA8: test2:
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; CORTEXA8: vneg.f32 d{{.*}}, d{{.*}}
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; CORTEXA9: test2:
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; CORTEXA9: vneg.f32 s{{.*}}, s{{.*}}
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