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ab043ff680
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
llvm-svn: 230794
56 lines
1.5 KiB
LLVM
56 lines
1.5 KiB
LLVM
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=ARM
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define i32 @t1(i32* nocapture %ptr) nounwind readonly {
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entry:
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; ARM: t1
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%add.ptr = getelementptr inbounds i32, i32* %ptr, i32 1
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%0 = load i32, i32* %add.ptr, align 4
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; ARM: ldr r{{[0-9]}}, [r0, #4]
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ret i32 %0
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}
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define i32 @t2(i32* nocapture %ptr) nounwind readonly {
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entry:
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; ARM: t2
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%add.ptr = getelementptr inbounds i32, i32* %ptr, i32 63
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%0 = load i32, i32* %add.ptr, align 4
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; ARM: ldr.w r{{[0-9]}}, [r0, #252]
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ret i32 %0
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}
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define zeroext i16 @t3(i16* nocapture %ptr) nounwind readonly {
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entry:
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; ARM: t3
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%add.ptr = getelementptr inbounds i16, i16* %ptr, i16 1
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%0 = load i16, i16* %add.ptr, align 4
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; ARM: ldrh r{{[0-9]}}, [r0, #2]
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ret i16 %0
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}
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define zeroext i16 @t4(i16* nocapture %ptr) nounwind readonly {
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entry:
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; ARM: t4
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%add.ptr = getelementptr inbounds i16, i16* %ptr, i16 63
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%0 = load i16, i16* %add.ptr, align 4
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; ARM: ldrh.w r{{[0-9]}}, [r0, #126]
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ret i16 %0
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}
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define zeroext i8 @t5(i8* nocapture %ptr) nounwind readonly {
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entry:
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; ARM: t5
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%add.ptr = getelementptr inbounds i8, i8* %ptr, i8 1
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%0 = load i8, i8* %add.ptr, align 4
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; ARM: ldrb r{{[0-9]}}, [r0, #1]
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ret i8 %0
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}
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define zeroext i8 @t6(i8* nocapture %ptr) nounwind readonly {
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entry:
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; ARM: t6
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%add.ptr = getelementptr inbounds i8, i8* %ptr, i8 63
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%0 = load i8, i8* %add.ptr, align 4
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; ARM: ldrb.w r{{[0-9]}}, [r0, #63]
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ret i8 %0
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}
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