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da52f0e643
As we introduced target triple environment amdgiz and amdgizcl, the address space values are no longer enums. We have to decide the value by target triple. The basic idea is to use struct AMDGPUAS to represent address space values. For address space values which are not depend on target triple, use static const members, so that they don't occupy extra memory space and is equivalent to a compile time constant. Since the struct is lightweight and cheap, it can be created on the fly at the point of usage. Or it can be added as member to a pass and created at the beginning of the run* function. Differential Revision: https://reviews.llvm.org/D31284 llvm-svn: 298846
68 lines
2.1 KiB
C++
68 lines
2.1 KiB
C++
//===- AMDGPUInstructionSelector --------------------------------*- C++ -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file declares the targeting of the InstructionSelector class for
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/// AMDGPU.
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
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#define LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
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#include "AMDGPU.h"
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#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/ADT/SmallVector.h"
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namespace llvm {
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class AMDGPUInstrInfo;
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class AMDGPURegisterBankInfo;
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class MachineInstr;
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class MachineOperand;
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class MachineRegisterInfo;
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class SIInstrInfo;
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class SIRegisterInfo;
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class SISubtarget;
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class AMDGPUInstructionSelector : public InstructionSelector {
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public:
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AMDGPUInstructionSelector(const SISubtarget &STI,
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const AMDGPURegisterBankInfo &RBI);
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bool select(MachineInstr &I) const override;
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private:
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struct GEPInfo {
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const MachineInstr &GEP;
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SmallVector<unsigned, 2> SgprParts;
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SmallVector<unsigned, 2> VgprParts;
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int64_t Imm;
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GEPInfo(const MachineInstr &GEP) : GEP(GEP), Imm(0) { }
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};
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MachineOperand getSubOperand64(MachineOperand &MO, unsigned SubIdx) const;
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bool selectG_CONSTANT(MachineInstr &I) const;
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bool selectG_ADD(MachineInstr &I) const;
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bool selectG_GEP(MachineInstr &I) const;
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bool hasVgprParts(ArrayRef<GEPInfo> AddrInfo) const;
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void getAddrModeInfo(const MachineInstr &Load, const MachineRegisterInfo &MRI,
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SmallVectorImpl<GEPInfo> &AddrInfo) const;
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bool selectSMRD(MachineInstr &I, ArrayRef<GEPInfo> AddrInfo) const;
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bool selectG_LOAD(MachineInstr &I) const;
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bool selectG_STORE(MachineInstr &I) const;
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const SIInstrInfo &TII;
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const SIRegisterInfo &TRI;
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const AMDGPURegisterBankInfo &RBI;
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protected:
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AMDGPUAS AMDGPUASI;
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};
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} // End llvm namespace.
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#endif
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