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f418c98924
Passes to fix three hardware errata that appear on some LEON processor variants. The instructions FSMULD, FMULS and FDIVS do not work as expected on some LEON processors. This change allows those instructions to be substituted for alternatives instruction sequences that are known to work. These passes only run when selected individually, or as part of a processor defintion. They are not included in general SPARC processor compilations for non-LEON processors or for those LEON processors that do not have these hardware errata. llvm-svn: 273108
21 lines
717 B
LLVM
Executable File
21 lines
717 B
LLVM
Executable File
; RUN: llc %s -O0 -march=sparc -mcpu=leon2 -o - | FileCheck %s
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; RUN: llc %s -O0 -march=sparc -mcpu=leon3 -o - | FileCheck %s
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; RUN: llc %s -O0 -march=sparc -mcpu=leon4 -o - | FileCheck %s
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; CHECK-LABEL: smac_test:
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; CHECK: smac %o1, %o0, %o0
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define i32 @smac_test(i16* %a, i16* %b) {
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entry:
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; %0 = tail call i32 asm sideeffect "smac $2, $1, $0", "={r2},{r3},{r4}"(i16* %a, i16* %b)
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%0 = tail call i32 asm sideeffect "smac $2, $1, $0", "=r,rI,r"(i16* %a, i16* %b)
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ret i32 %0
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}
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; CHECK-LABEL: umac_test:
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; CHECK: umac %o1, %o0, %o0
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define i32 @umac_test(i16* %a, i16* %b) {
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entry:
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%0 = tail call i32 asm sideeffect "umac $2, $1, $0", "=r,rI,r"(i16* %a, i16* %b)
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ret i32 %0
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}
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