mirror of
https://github.com/RPCS3/llvm-mirror.git
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a52916b4b8
Summary:
G_LOAD/G_STORE, add alternative RegisterBank mapping.
For G_LOAD, Fast and Greedy mode choose the same RegisterBank mapping (GprRegBank ) for the G_GLOAD + G_FADD , can't get rid of cross register bank copy GprRegBank->VecRegBank.
Reviewers: zvi, rovka, qcolombet, ab
Reviewed By: zvi
Subscribers: llvm-commits, dberris, kristof.beyls, eladcohen, guyblank
Differential Revision: https://reviews.llvm.org/D30979
llvm-svn: 298907
187 lines
5.1 KiB
LLVM
187 lines
5.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=x86_64-linux-gnu -global-isel < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=SSE
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; RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -global-isel < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=ALL_AVX --check-prefix=AVX
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; RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -global-isel < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=ALL_AVX --check-prefix=AVX512F
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; RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -mattr=+avx512vl -global-isel < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=ALL_AVX --check-prefix=AVX512VL
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define i64 @test_add_i64(i64 %arg1, i64 %arg2) {
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; ALL-LABEL: test_add_i64:
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; ALL: # BB#0:
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; ALL-NEXT: leaq (%rsi,%rdi), %rax
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; ALL-NEXT: retq
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%ret = add i64 %arg1, %arg2
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ret i64 %ret
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}
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define i32 @test_add_i32(i32 %arg1, i32 %arg2) {
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; ALL-LABEL: test_add_i32:
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; ALL: # BB#0:
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; ALL-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
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; ALL-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
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; ALL-NEXT: leal (%rsi,%rdi), %eax
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; ALL-NEXT: retq
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%ret = add i32 %arg1, %arg2
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ret i32 %ret
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}
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define i64 @test_sub_i64(i64 %arg1, i64 %arg2) {
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; ALL-LABEL: test_sub_i64:
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; ALL: # BB#0:
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; ALL-NEXT: subq %rsi, %rdi
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; ALL-NEXT: movq %rdi, %rax
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; ALL-NEXT: retq
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%ret = sub i64 %arg1, %arg2
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ret i64 %ret
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}
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define i32 @test_sub_i32(i32 %arg1, i32 %arg2) {
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; ALL-LABEL: test_sub_i32:
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; ALL: # BB#0:
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; ALL-NEXT: subl %esi, %edi
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; ALL-NEXT: movl %edi, %eax
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; ALL-NEXT: retq
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%ret = sub i32 %arg1, %arg2
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ret i32 %ret
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}
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define float @test_add_float(float %arg1, float %arg2) {
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; SSE-LABEL: test_add_float:
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; SSE: # BB#0:
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; SSE-NEXT: addss %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; ALL_AVX-LABEL: test_add_float:
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; ALL_AVX: # BB#0:
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; ALL_AVX-NEXT: vaddss %xmm1, %xmm0, %xmm0
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; ALL_AVX-NEXT: retq
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%ret = fadd float %arg1, %arg2
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ret float %ret
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}
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define double @test_add_double(double %arg1, double %arg2) {
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; SSE-LABEL: test_add_double:
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; SSE: # BB#0:
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; SSE-NEXT: addsd %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; ALL_AVX-LABEL: test_add_double:
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; ALL_AVX: # BB#0:
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; ALL_AVX-NEXT: vaddsd %xmm1, %xmm0, %xmm0
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; ALL_AVX-NEXT: retq
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%ret = fadd double %arg1, %arg2
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ret double %ret
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}
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define float @test_sub_float(float %arg1, float %arg2) {
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; SSE-LABEL: test_sub_float:
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; SSE: # BB#0:
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; SSE-NEXT: subss %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; ALL_AVX-LABEL: test_sub_float:
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; ALL_AVX: # BB#0:
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; ALL_AVX-NEXT: vsubss %xmm1, %xmm0, %xmm0
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; ALL_AVX-NEXT: retq
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%ret = fsub float %arg1, %arg2
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ret float %ret
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}
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define double @test_sub_double(double %arg1, double %arg2) {
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; SSE-LABEL: test_sub_double:
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; SSE: # BB#0:
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; SSE-NEXT: subsd %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; ALL_AVX-LABEL: test_sub_double:
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; ALL_AVX: # BB#0:
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; ALL_AVX-NEXT: vsubsd %xmm1, %xmm0, %xmm0
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; ALL_AVX-NEXT: retq
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%ret = fsub double %arg1, %arg2
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ret double %ret
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}
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define <4 x i32> @test_add_v4i32(<4 x i32> %arg1, <4 x i32> %arg2) {
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; SSE-LABEL: test_add_v4i32:
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; SSE: # BB#0:
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; SSE-NEXT: paddd %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; ALL_AVX-LABEL: test_add_v4i32:
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; ALL_AVX: # BB#0:
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; ALL_AVX-NEXT: vpaddd %xmm1, %xmm0, %xmm0
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; ALL_AVX-NEXT: retq
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%ret = add <4 x i32> %arg1, %arg2
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ret <4 x i32> %ret
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}
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define <4 x i32> @test_sub_v4i32(<4 x i32> %arg1, <4 x i32> %arg2) {
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; SSE-LABEL: test_sub_v4i32:
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; SSE: # BB#0:
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; SSE-NEXT: psubd %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; ALL_AVX-LABEL: test_sub_v4i32:
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; ALL_AVX: # BB#0:
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; ALL_AVX-NEXT: vpsubd %xmm1, %xmm0, %xmm0
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; ALL_AVX-NEXT: retq
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%ret = sub <4 x i32> %arg1, %arg2
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ret <4 x i32> %ret
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}
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define <4 x float> @test_add_v4f32(<4 x float> %arg1, <4 x float> %arg2) {
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; SSE-LABEL: test_add_v4f32:
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; SSE: # BB#0:
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; SSE-NEXT: addps %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; ALL_AVX-LABEL: test_add_v4f32:
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; ALL_AVX: # BB#0:
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; ALL_AVX-NEXT: vaddps %xmm1, %xmm0, %xmm0
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; ALL_AVX-NEXT: retq
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%ret = fadd <4 x float> %arg1, %arg2
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ret <4 x float> %ret
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}
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define <4 x float> @test_sub_v4f32(<4 x float> %arg1, <4 x float> %arg2) {
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; SSE-LABEL: test_sub_v4f32:
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; SSE: # BB#0:
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; SSE-NEXT: subps %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; ALL_AVX-LABEL: test_sub_v4f32:
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; ALL_AVX: # BB#0:
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; ALL_AVX-NEXT: vsubps %xmm1, %xmm0, %xmm0
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; ALL_AVX-NEXT: retq
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%ret = fsub <4 x float> %arg1, %arg2
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ret <4 x float> %ret
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}
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define i32 @test_copy_float(float %val) {
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; SSE-LABEL: test_copy_float:
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; SSE: # BB#0:
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; SSE-NEXT: movd %xmm0, %eax
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; SSE-NEXT: retq
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;
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; ALL_AVX-LABEL: test_copy_float:
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; ALL_AVX: # BB#0:
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; ALL_AVX-NEXT: vmovd %xmm0, %eax
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; ALL_AVX-NEXT: retq
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%r = bitcast float %val to i32
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ret i32 %r
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}
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define float @test_copy_i32(i32 %val) {
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; SSE-LABEL: test_copy_i32:
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; SSE: # BB#0:
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; SSE-NEXT: movd %edi, %xmm0
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; SSE-NEXT: retq
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;
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; ALL_AVX-LABEL: test_copy_i32:
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; ALL_AVX: # BB#0:
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; ALL_AVX-NEXT: vmovd %edi, %xmm0
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; ALL_AVX-NEXT: retq
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%r = bitcast i32 %val to float
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ret float %r
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}
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