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6d132686e0
Summary:
Currently, when 't1: i1 = setcc t2, t3, cc' followed by 't4: i1 = xor t1, Constant:i1<-1>' is folded into 't5: i1 = setcc t2, t3 !cc', SDLoc of newly created SDValue 't5' follows SDLoc of 't4', not 't1'. However, as the opcode of newly created SDValue is 'setcc', it make more sense to take DebugLoc from 't1' than 't4'. For the code below
```
extern int bar();
extern int baz();
int foo(int x, int y) {
if (x != y)
return bar();
else
return baz();
}
```
, following is the bitcode representation of 'foo' at the end of llvm-ir level optimization:
```
define i32 @foo(i32 %x, i32 %y) !dbg !4 {
entry:
tail call void @llvm.dbg.value(metadata i32 %x, i64 0, metadata !9, metadata !11), !dbg !12
tail call void @llvm.dbg.value(metadata i32 %y, i64 0, metadata !10, metadata !11), !dbg !13
%cmp = icmp ne i32 %x, %y, !dbg !14
br i1 %cmp, label %if.then, label %if.else, !dbg !16
if.then: ; preds = %entry
%call = tail call i32 (...) @bar() #3, !dbg !17
br label %return, !dbg !18
if.else: ; preds = %entry
%call1 = tail call i32 (...) @baz() #3, !dbg !19
br label %return, !dbg !20
return: ; preds = %if.else, %if.then
%retval.0 = phi i32 [ %call, %if.then ], [ %call1, %if.else ]
ret i32 %retval.0, !dbg !21
}
!14 = !DILocation(line: 5, column: 9, scope: !15)
!16 = !DILocation(line: 5, column: 7, scope: !4)
```
As you can see, in 'entry' block, 'icmp' instruction and 'br' instruction have different debug locations. However, with current implementation, there's no distinction between debug locations of these two when they are lowered to asm instructions. This is because 'icmp' and 'br' become 'setcc' 'xor' and 'brcond' in SelectionDAG, where SDLoc of 'setcc' follows the debug location of 'icmp' but SDLOC of 'xor' and 'brcond' follows the debug location of 'br' instruction, and SDLoc of 'xor' overwrites SDLoc of 'setcc' when they are folded. This patch addresses this issue.
Reviewers: atrick, bogner, andreadb, craig.topper, aprantl
Reviewed By: andreadb
Subscribers: jlebar, mkuper, jholewinski, andreadb, llvm-commits
Differential Revision: https://reviews.llvm.org/D29813
llvm-svn: 296825
182 lines
4.0 KiB
LLVM
182 lines
4.0 KiB
LLVM
; RUN: llc -mtriple=i686-unknown -verify-machineinstrs < %s | FileCheck %s
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; RUN: opt < %s -codegenprepare -S -mtriple=x86_64-unknown-unknown | FileCheck --check-prefix=CHECK-CGP %s
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@A = global i32 zeroinitializer
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@B = global i32 zeroinitializer
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@C = global i32 zeroinitializer
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; Test that 'and' is sunk into bb0.
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define i32 @and_sink1(i32 %a, i1 %c) {
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; CHECK-LABEL: and_sink1:
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; CHECK: testb $1,
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; CHECK: je
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; CHECK-NOT: andl $4,
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; CHECK: movl $0, A
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; CHECK: testb $4,
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; CHECK: jne
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; CHECK-CGP-LABEL: @and_sink1(
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; CHECK-CGP-NOT: and i32
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%and = and i32 %a, 4
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br i1 %c, label %bb0, label %bb2
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bb0:
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; CHECK-CGP-LABEL: bb0:
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; CHECK-CGP: and i32
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; CHECK-CGP-NEXT: icmp eq i32
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; CHECK-CGP-NEXT: store
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; CHECK-CGP-NEXT: br
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%cmp = icmp eq i32 %and, 0
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store i32 0, i32* @A
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br i1 %cmp, label %bb1, label %bb2
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bb1:
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ret i32 1
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bb2:
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ret i32 0
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}
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; Test that both 'and' and cmp get sunk to bb1.
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define i32 @and_sink2(i32 %a, i1 %c, i1 %c2) {
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; CHECK-LABEL: and_sink2:
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; CHECK: movl $0, A
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; CHECK: testb $1,
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; CHECK: je
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; CHECK-NOT: andl $4,
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; CHECK: movl $0, B
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; CHECK: testb $1,
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; CHECK: je
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; CHECK: movl $0, C
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; CHECK: testb $4,
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; CHECK: jne
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; CHECK-CGP-LABEL: @and_sink2(
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; CHECK-CGP-NOT: and i32
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%and = and i32 %a, 4
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store i32 0, i32* @A
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br i1 %c, label %bb0, label %bb3
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bb0:
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; CHECK-CGP-LABEL: bb0:
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; CHECK-CGP-NOT: and i32
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; CHECK-CGP-NOT: icmp
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%cmp = icmp eq i32 %and, 0
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store i32 0, i32* @B
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br i1 %c2, label %bb1, label %bb3
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bb1:
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; CHECK-CGP-LABEL: bb1:
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; CHECK-CGP: and i32
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; CHECK-CGP-NEXT: icmp eq i32
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; CHECK-CGP-NEXT: store
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; CHECK-CGP-NEXT: br
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store i32 0, i32* @C
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br i1 %cmp, label %bb2, label %bb0
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bb2:
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ret i32 1
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bb3:
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ret i32 0
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}
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; Test that CodeGenPrepare doesn't get stuck in a loop sinking and hoisting a masked load.
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define i32 @and_sink3(i1 %c, i32* %p) {
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; CHECK-LABEL: and_sink3:
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; CHECK: testb $1,
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; CHECK: je
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; CHECK: movzbl
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; CHECK-DAG: movl $0, A
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; CHECK-DAG: testl %
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; CHECK: je
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; CHECK-CGP-LABEL: @and_sink3(
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; CHECK-CGP: load i32
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; CHECK-CGP-NEXT: and i32
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%load = load i32, i32* %p
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%and = and i32 %load, 255
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br i1 %c, label %bb0, label %bb2
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bb0:
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; CHECK-CGP-LABEL: bb0:
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; CHECK-CGP-NOT: and i32
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; CHECK-CGP: icmp eq i32
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%cmp = icmp eq i32 %and, 0
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store i32 0, i32* @A
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br i1 %cmp, label %bb1, label %bb2
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bb1:
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ret i32 1
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bb2:
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ret i32 0
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}
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; Test that CodeGenPrepare sinks/duplicates non-immediate 'and'.
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define i32 @and_sink4(i32 %a, i32 %b, i1 %c) {
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; CHECK-LABEL: and_sink4:
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; CHECK: testb $1,
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; CHECK: je
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; CHECK-NOT: andl
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; CHECK-DAG: movl $0, A
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; CHECK-DAG: testl [[REG1:%[a-z0-9]+]], [[REG2:%[a-z0-9]+]]
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; CHECK: jne
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; CHECK-DAG: movl {{%[a-z0-9]+}}, B
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; CHECK-DAG: testl [[REG1]], [[REG2]]
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; CHECK: je
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; CHECK-CGP-LABEL: @and_sink4(
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; CHECK-CGP-NOT: and i32
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; CHECK-CGP-NOT: icmp
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%and = and i32 %a, %b
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%cmp = icmp eq i32 %and, 0
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br i1 %c, label %bb0, label %bb3
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bb0:
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; CHECK-CGP-LABEL: bb0:
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; CHECK-CGP: and i32
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; CHECK-CGP-NEXT: icmp eq i32
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store i32 0, i32* @A
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br i1 %cmp, label %bb1, label %bb3
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bb1:
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; CHECK-CGP-LABEL: bb1:
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; CHECK-CGP: and i32
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; CHECK-CGP-NEXT: icmp eq i32
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%add = add i32 %a, %b
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store i32 %add, i32* @B
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br i1 %cmp, label %bb2, label %bb3
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bb2:
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ret i32 1
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bb3:
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ret i32 0
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}
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; Test that CodeGenPrepare doesn't sink/duplicate non-immediate 'and'
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; when it would increase register pressure.
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define i32 @and_sink5(i32 %a, i32 %b, i32 %a2, i32 %b2, i1 %c) {
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; CHECK-LABEL: and_sink5:
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; CHECK: testb $1,
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; CHECK: je
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; CHECK-DAG: andl {{[0-9]+\(%[a-z0-9]+\)}}, [[REG:%[a-z0-9]+]]
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; CHECK-DAG: movl $0, A
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; CHECK: jne
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; CHECK-DAG: movl {{%[a-z0-9]+}}, B
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; CHECK-DAG: testl [[REG]], [[REG]]
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; CHECK: je
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; CHECK-CGP-LABEL: @and_sink5(
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; CHECK-CGP: and i32
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; CHECK-CGP-NOT: icmp
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%and = and i32 %a, %b
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%cmp = icmp eq i32 %and, 0
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br i1 %c, label %bb0, label %bb3
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bb0:
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; CHECK-CGP-LABEL: bb0:
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; CHECK-CGP-NOT: and i32
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; CHECK-CGP: icmp eq i32
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store i32 0, i32* @A
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br i1 %cmp, label %bb1, label %bb3
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bb1:
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; CHECK-CGP-LABEL: bb1:
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; CHECK-CGP-NOT: and i32
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; CHECK-CGP: icmp eq i32
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%add = add i32 %a2, %b2
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store i32 %add, i32* @B
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br i1 %cmp, label %bb2, label %bb3
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bb2:
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ret i32 1
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bb3:
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ret i32 0
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}
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