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09a65b6f28
Handle the case where a sign extension has ended up being split into separate stages (typically to get around vector legal ops) and a zext + sext_in_reg gets inserted. Differential Revision: https://reviews.llvm.org/D27461 llvm-svn: 288842
47 lines
1.7 KiB
LLVM
47 lines
1.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX
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; fold sextinreg(zext) -> sext
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define <4 x i64> @sextinreg_zext_v16i8_4i64(<16 x i8> %a0) {
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; SSE-LABEL: sextinreg_zext_v16i8_4i64:
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; SSE: # BB#0:
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; SSE-NEXT: pmovsxbq %xmm0, %xmm2
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; SSE-NEXT: psrld $16, %xmm0
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; SSE-NEXT: pmovsxbq %xmm0, %xmm1
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; SSE-NEXT: movdqa %xmm2, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: sextinreg_zext_v16i8_4i64:
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; AVX: # BB#0:
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; AVX-NEXT: vpmovsxbq %xmm0, %ymm0
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; AVX-NEXT: retq
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%1 = shufflevector <16 x i8> %a0, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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%2 = zext <4 x i8> %1 to <4 x i64>
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%3 = shl <4 x i64> %2, <i64 56, i64 56, i64 56, i64 56>
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%4 = ashr <4 x i64> %3, <i64 56, i64 56, i64 56, i64 56>
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ret <4 x i64> %4
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}
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; fold sextinreg(zext(sext)) -> sext
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define <4 x i64> @sextinreg_zext_sext_v16i8_4i64(<16 x i8> %a0) {
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; SSE-LABEL: sextinreg_zext_sext_v16i8_4i64:
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; SSE: # BB#0:
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; SSE-NEXT: pmovsxbq %xmm0, %xmm2
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; SSE-NEXT: psrld $16, %xmm0
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; SSE-NEXT: pmovsxbq %xmm0, %xmm1
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; SSE-NEXT: movdqa %xmm2, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: sextinreg_zext_sext_v16i8_4i64:
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; AVX: # BB#0:
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; AVX-NEXT: vpmovsxbq %xmm0, %ymm0
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; AVX-NEXT: retq
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%1 = shufflevector <16 x i8> %a0, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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%2 = sext <4 x i8> %1 to <4 x i32>
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%3 = zext <4 x i32> %2 to <4 x i64>
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%4 = shl <4 x i64> %3, <i64 32, i64 32, i64 32, i64 32>
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%5 = ashr <4 x i64> %4, <i64 32, i64 32, i64 32, i64 32>
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ret <4 x i64> %5
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}
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