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ab371a9d51
- corrected DS_GWS_* opcodes (see VI_Shader_Programming#16.pdf for detailed description) - address operand is not used - several opcodes have data operand - all opcodes have offset modifier - DS_AND_SRC2_B32: corrected typo in mnemo - DS_WRAP_RTN_F32 replaced with DS_WRAP_RTN_B32 - added CI/VI opcodes: - DS_CONDXCHG32_RTN_B64 - DS_GWS_SEMA_RELEASE_ALL - added VI opcodes: - DS_CONSUME - DS_APPEND - DS_ORDERED_COUNT Differential Revision: https://reviews.llvm.org/D31707 llvm-svn: 299767
42 lines
1.4 KiB
ArmAsm
42 lines
1.4 KiB
ArmAsm
// RUN: llvm-mc -arch=amdgcn -mcpu=fiji -show-encoding %s | FileCheck %s --check-prefix=VI
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.globl global
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.globl gds
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// Parse a global expression
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s_mov_b32 s0, global
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// VI: s_mov_b32 s0, global ; encoding: [0xff,0x00,0x80,0xbe,A,A,A,A]
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// VI-NEXT: ; fixup A - offset: 4, value: global, kind: FK_PCRel_4
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// Use a token with the same name as a global
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ds_gws_init v2 gds
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// VI: ds_gws_init v2 gds ; encoding: [0x00,0x00,0x33,0xd9,0x00,0x02,0x00,0x00]
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// Use a global with the same name as a token
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s_mov_b32 s0, gds
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// VI: s_mov_b32 s0, gds ; encoding: [0xff,0x00,0x80,0xbe,A,A,A,A]
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// VI-NEXT: ; fixup A - offset: 4, value: gds, kind: FK_PCRel_4
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// Use a binary expression
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s_mov_b32 s0, gds+4
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// VI: s_mov_b32 s0, gds+4 ; encoding: [0xff,0x00,0x80,0xbe,A,A,A,A]
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// VI-NEXT: ; fixup A - offset: 4, value: gds+4, kind: FK_PCRel_4
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// Consecutive instructions with no blank line in between to make sure we
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// don't call Lex() too many times.
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s_add_u32 s0, s0, global+4
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s_addc_u32 s1, s1, 0
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// VI: s_add_u32 s0, s0, global+4
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// VI: s_addc_u32 s1, s1, 0
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// Use a computed expression that results in an inline immediate.
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.set foo, 4
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s_mov_b32 s0, foo+2
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// VI: s_mov_b32 s0, 6 ; encoding: [0x86,0x00,0x80,0xbe]
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// Use a computed expression that results in a non-inline immediate.
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.set foo, 512
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s_mov_b32 s0, foo+2
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// VI: s_mov_b32 s0, 514 ; encoding: [0xff,0x00,0x80,0xbe,0x02,0x02,0x00,0x00]
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