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llvm-mirror/test/MC/AMDGPU/vop1.s
Sam Kolton 94d1ca9e9c AMDGPU] Assembler: better support for immediate literals in assembler. 
Summary:
Prevously assembler parsed all literals as either 32-bit integers or 32-bit floating-point values. Because of this we couldn't support f64 literals.
E.g. in instruction "v_fract_f64 v[0:1], 0.5", literal 0.5 was encoded as 32-bit literal 0x3f000000, which is incorrect and will be interpreted as 3.0517578125E-5 instead of 0.5. Correct encoding is inline constant 240 (optimal) or 32-bit literal 0x3FE00000 at least.

With this change the way immediate literals are parsed is changed. All literals are always parsed as 64-bit values either integer or floating-point. Then we convert parsed literals to correct form based on information about type of operand parsed (was literal floating or binary) and type of expected instruction operands (is this f32/64 or b32/64 instruction).
Here are rules how we convert literals:
    - We parsed fp literal:
        - Instruction expects 64-bit operand:
            - If parsed literal is inlinable (e.g. v_fract_f64_e32 v[0:1], 0.5)
                - then we do nothing this literal
            - Else if literal is not-inlinable but instruction requires to inline it (e.g. this is e64 encoding, v_fract_f64_e64 v[0:1], 1.5)
                - report error
            - Else literal is not-inlinable but we can encode it as additional 32-bit literal constant
                - If instruction expect fp operand type (f64)
                    - Check if low 32 bits of literal are zeroes (e.g. v_fract_f64 v[0:1], 1.5)
                        - If so then do nothing
                    - Else (e.g. v_fract_f64 v[0:1], 3.1415)
                        - report warning that low 32 bits will be set to zeroes and precision will be lost
                        - set low 32 bits of literal to zeroes
                - Instruction expects integer operand type (e.g. s_mov_b64_e32 s[0:1], 1.5)
                    - report error as it is unclear how to encode this literal
        - Instruction expects 32-bit operand:
            - Convert parsed 64 bit fp literal to 32 bit fp. Allow lose of precision but not overflow or underflow
            - Is this literal inlinable and are we required to inline literal (e.g. v_trunc_f32_e64 v0, 0.5)
                - do nothing
                - Else report error
            - Do nothing. We can encode any other 32-bit fp literal (e.g. v_trunc_f32 v0, 10000000.0)
    - Parsed binary literal:
        - Is this literal inlinable (e.g. v_trunc_f32_e32 v0, 35)
            - do nothing
        - Else, are we required to inline this literal (e.g. v_trunc_f32_e64 v0, 35)
            - report error
        - Else, literal is not-inlinable and we are not required to inline it
            - Are high 32 bit of literal zeroes or same as sign bit (32 bit)
                - do nothing (e.g. v_trunc_f32 v0, 0xdeadbeef)
            - Else
                - report error (e.g. v_trunc_f32 v0, 0x123456789abcdef0)

For this change it is required that we know operand types of instruction (are they f32/64 or b32/64). I added several new register operands (they extend previous register operands) and set operand types to corresponding types:
'''
enum OperandType {
    OPERAND_REG_IMM32_INT,
    OPERAND_REG_IMM32_FP,
    OPERAND_REG_INLINE_C_INT,
    OPERAND_REG_INLINE_C_FP,
}
'''

This is not working yet:
    - Several tests are failing
    - Problems with predicate methods for inline immediates
    - LLVM generated assembler parts try to select e64 encoding before e32.
More changes are required for several AsmOperands.

Reviewers: vpykhtin, tstellarAMD

Subscribers: arsenm, kzhuravl, artem.tamazov

Differential Revision: https://reviews.llvm.org/D22922

llvm-svn: 281050
2016-09-09 14:44:04 +00:00

377 lines
14 KiB
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Raw Blame History

// RUN: not llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=SI --check-prefix=SICI
// RUN: not llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=SI --check-prefix=SICI
// RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=SICI --check-prefix=CIVI
// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=CIVI --check-prefix=VI
// RUN: not llvm-mc -arch=amdgcn -show-encoding %s 2>&1 | FileCheck %s --check-prefix=NOSI --check-prefix=NOSICI
// RUN: not llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s 2>&1 | FileCheck %s --check-prefix=NOSI --check-prefix=NOSICI
// RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s 2>&1 | FileCheck %s --check-prefix=NOSICI
// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s 2>&1 | FileCheck %s -check-prefix=NOVI
// Force 32-bit encoding
// GCN: v_mov_b32_e32 v1, v2 ; encoding: [0x02,0x03,0x02,0x7e]
v_mov_b32_e32 v1, v2
// Force 32-bit encoding for special instructions
// FIXME: We should be printing _e32 suffixes for these:
// GCN: v_nop ; encoding: [0x00,0x00,0x00,0x7e]
v_nop_e32
// SICI: v_clrexcp ; encoding: [0x00,0x82,0x00,0x7e]
// VI: v_clrexcp ; encoding: [0x00,0x6a,0x00,0x7e]
v_clrexcp_e32
//===----------------------------------------------------------------------===//
// Instructions
//===----------------------------------------------------------------------===//
// GCN: v_nop ; encoding: [0x00,0x00,0x00,0x7e]
v_nop
// GCN: v_mov_b32_e32 v1, v2 ; encoding: [0x02,0x03,0x02,0x7e]
v_mov_b32_e32 v1, v2
// GCN: v_readfirstlane_b32 s1, v2 ; encoding: [0x02,0x05,0x02,0x7e]
v_readfirstlane_b32 s1, v2
// GCN: v_cvt_i32_f64_e32 v1, v[2:3] ; encoding: [0x02,0x07,0x02,0x7e]
v_cvt_i32_f64_e32 v1, v[2:3]
// GCN: v_cvt_f64_i32_e32 v[1:2], v2 ; encoding: [0x02,0x09,0x02,0x7e]
v_cvt_f64_i32_e32 v[1:2], v2
// GCN: v_cvt_f32_i32_e32 v1, v2 ; encoding: [0x02,0x0b,0x02,0x7e]
v_cvt_f32_i32_e32 v1, v2
// GCN: v_cvt_f32_u32_e32 v1, v2 ; encoding: [0x02,0x0d,0x02,0x7e]
v_cvt_f32_u32_e32 v1, v2
// GCN: v_cvt_u32_f32_e32 v1, v2 ; encoding: [0x02,0x0f,0x02,0x7e
v_cvt_u32_f32_e32 v1, v2
// GCN: v_cvt_i32_f32_e32 v1, v2 ; encoding: [0x02,0x11,0x02,0x7e]
v_cvt_i32_f32_e32 v1, v2
// SICI: v_mov_fed_b32_e32 v1, v2 ; encoding: [0x02,0x13,0x02,0x7e]
// NOVI: error: instruction not supported on this GPU
v_mov_fed_b32_e32 v1, v2
// GCN: v_cvt_f16_f32_e32 v1, v2 ; encoding: [0x02,0x15,0x02,0x7e]
v_cvt_f16_f32_e32 v1, v2
// GCN: v_cvt_f32_f16_e32 v1, v2 ; encoding: [0x02,0x17,0x02,0x7e]
v_cvt_f32_f16_e32 v1, v2
// GCN: v_cvt_rpi_i32_f32_e32 v1, v2 ; encoding: [0x02,0x19,0x02,0x7e]
v_cvt_rpi_i32_f32_e32 v1, v2
// GCN: v_cvt_flr_i32_f32_e32 v1, v2 ; encoding: [0x02,0x1b,0x02,0x7e]
v_cvt_flr_i32_f32_e32 v1, v2
// GCN: v_cvt_off_f32_i4_e32 v1, v2 ; encoding: [0x02,0x1d,0x02,0x7e]
v_cvt_off_f32_i4_e32 v1, v2
// GCN: v_cvt_f32_f64_e32 v1, v[2:3] ; encoding: [0x02,0x1f,0x02,0x7e]
v_cvt_f32_f64_e32 v1, v[2:3]
// GCN: v_cvt_f64_f32_e32 v[1:2], v2 ; encoding: [0x02,0x21,0x02,0x7e]
v_cvt_f64_f32_e32 v[1:2], v2
// GCN: v_cvt_f32_ubyte0_e32 v1, v2 ; encoding: [0x02,0x23,0x02,0x7e]
v_cvt_f32_ubyte0_e32 v1, v2
// GCN: v_cvt_f32_ubyte1_e32 v1, v2 ; encoding: [0x02,0x25,0x02,0x7e]
v_cvt_f32_ubyte1_e32 v1, v2
// GCN: v_cvt_f32_ubyte2_e32 v1, v2 ; encoding: [0x02,0x27,0x02,0x7e]
v_cvt_f32_ubyte2_e32 v1, v2
// GCN: v_cvt_f32_ubyte3_e32 v1, v2 ; encoding: [0x02,0x29,0x02,0x7e]
v_cvt_f32_ubyte3_e32 v1, v2
// GCN: v_cvt_u32_f64_e32 v1, v[2:3] ; encoding: [0x02,0x2b,0x02,0x7e]
v_cvt_u32_f64_e32 v1, v[2:3]
// GCN: v_cvt_f64_u32_e32 v[1:2], v2 ; encoding: [0x02,0x2d,0x02,0x7e]
v_cvt_f64_u32_e32 v[1:2], v2
// NOSI: error: instruction not supported on this GPU
// NOSI: v_trunc_f64_e32 v[1:2], v[2:3]
// CIVI: v_trunc_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x2f,0x02,0x7e]
v_trunc_f64_e32 v[1:2], v[2:3]
// NOSI: error: instruction not supported on this GPU
// NOSI: v_ceil_f64_e32 v[1:2], v[2:3]
// CIVI: v_ceil_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x31,0x02,0x7e]
v_ceil_f64_e32 v[1:2], v[2:3]
// NOSI: error: instruction not supported on this GPU
// NOSI: v_rndne_f64_e32 v[1:2], v[2:3]
// CIVI: v_rndne_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x33,0x02,0x7e]
v_rndne_f64_e32 v[1:2], v[2:3]
// NOSI: error: instruction not supported on this GPU
// NOSI: v_floor_f64_e32 v[1:2], v[2:3]
// CIVI: v_floor_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x35,0x02,0x7e]
v_floor_f64_e32 v[1:2], v[2:3]
// SICI: v_fract_f32_e32 v1, v2 ; encoding: [0x02,0x41,0x02,0x7e]
// VI: v_fract_f32_e32 v1, v2 ; encoding: [0x02,0x37,0x02,0x7e]
v_fract_f32 v1, v2
// SICI: v_trunc_f32_e32 v1, v2 ; encoding: [0x02,0x43,0x02,0x7e]
// VI: v_trunc_f32_e32 v1, v2 ; encoding: [0x02,0x39,0x02,0x7e]
v_trunc_f32 v1, v2
// SICI: v_ceil_f32_e32 v1, v2 ; encoding: [0x02,0x45,0x02,0x7e]
// VI: v_ceil_f32_e32 v1, v2 ; encoding: [0x02,0x3b,0x02,0x7e]
v_ceil_f32 v1, v2
// SICI: v_rndne_f32_e32 v1, v2 ; encoding: [0x02,0x47,0x02,0x7e]
// VI: v_rndne_f32_e32 v1, v2 ; encoding: [0x02,0x3d,0x02,0x7e]
v_rndne_f32 v1, v2
// SICI: v_floor_f32_e32 v1, v2 ; encoding: [0x02,0x49,0x02,0x7e]
// VI: v_floor_f32_e32 v1, v2 ; encoding: [0x02,0x3f,0x02,0x7e]
v_floor_f32_e32 v1, v2
// SICI: v_exp_f32_e32 v1, v2 ; encoding: [0x02,0x4b,0x02,0x7e]
// VI: v_exp_f32_e32 v1, v2 ; encoding: [0x02,0x41,0x02,0x7e]
v_exp_f32 v1, v2
// SICI: v_log_clamp_f32_e32 v1, v2 ; encoding: [0x02,0x4d,0x02,0x7e]
// NOVI: error: instruction not supported on this GPU
// NOVI: v_log_clamp_f32 v1, v2
v_log_clamp_f32 v1, v2
// SICI: v_log_f32_e32 v1, v2 ; encoding: [0x02,0x4f,0x02,0x7e]
// VI: v_log_f32_e32 v1, v2 ; encoding: [0x02,0x43,0x02,0x7e]
v_log_f32 v1, v2
// SICI: v_rcp_clamp_f32_e32 v1, v2 ; encoding: [0x02,0x51,0x02,0x7e]
// NOVI: error: instruction not supported on this GPU
// NOVI: v_rcp_clamp_f32 v1, v2
v_rcp_clamp_f32 v1, v2
// SICI: v_rcp_legacy_f32_e32 v1, v2 ; encoding: [0x02,0x53,0x02,0x7e]
// NOVI: error: instruction not supported on this GPU
// NOVI: v_rcp_legacy_f32 v1, v2
v_rcp_legacy_f32 v1, v2
// SICI: v_rcp_f32_e32 v1, v2 ; encoding: [0x02,0x55,0x02,0x7e]
// VI: v_rcp_f32_e32 v1, v2 ; encoding: [0x02,0x45,0x02,0x7e]
v_rcp_f32 v1, v2
// SICI: v_rcp_iflag_f32_e32 v1, v2 ; encoding: [0x02,0x57,0x02,0x7e]
// VI: v_rcp_iflag_f32_e32 v1, v2 ; encoding: [0x02,0x47,0x02,0x7e]
v_rcp_iflag_f32 v1, v2
// SICI: v_rsq_clamp_f32_e32 v1, v2 ; encoding: [0x02,0x59,0x02,0x7e]
// NOVI: error: instruction not supported on this GPU
// NOVI: v_rsq_clamp_f32 v1, v2
v_rsq_clamp_f32 v1, v2
// SICI: v_rsq_legacy_f32_e32 v1, v2 ; encoding: [0x02,0x5b,0x02,0x7e]
// NOVI: error: instruction not supported on this GPU
// NOVI: v_rsq_legacy_f32 v1, v2
v_rsq_legacy_f32 v1, v2
// SICI: v_rsq_f32_e32 v1, v2 ; encoding: [0x02,0x5d,0x02,0x7e]
// VI: v_rsq_f32_e32 v1, v2 ; encoding: [0x02,0x49,0x02,0x7e]
v_rsq_f32_e32 v1, v2
// SICI: v_rcp_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x5f,0x02,0x7e]
// VI: v_rcp_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x4b,0x02,0x7e]
v_rcp_f64 v[1:2], v[2:3]
// SICI: v_rcp_clamp_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x61,0x02,0x7e]
// NOVI: error: instruction not supported on this GPU
// NOVI: v_rcp_clamp_f64 v[1:2], v[2:3]
v_rcp_clamp_f64 v[1:2], v[2:3]
// SICI: v_rsq_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x63,0x02,0x7e]
// VI: v_rsq_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x4d,0x02,0x7e]
v_rsq_f64 v[1:2], v[2:3]
// SICI: v_rsq_clamp_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x65,0x02,0x7e]
// NOVI: error: instruction not supported on this GPU
// NOVI: v_rsq_clamp_f64 v[1:2], v[2:3]
v_rsq_clamp_f64 v[1:2], v[2:3]
// SICI: v_sqrt_f32_e32 v1, v2 ; encoding: [0x02,0x67,0x02,0x7e]
// VI: v_sqrt_f32_e32 v1, v2 ; encoding: [0x02,0x4f,0x02,0x7e]
v_sqrt_f32 v1, v2
// SICI: v_sqrt_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x69,0x02,0x7e]
// VI: v_sqrt_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x51,0x02,0x7e]
v_sqrt_f64 v[1:2], v[2:3]
// SICI: v_sin_f32_e32 v1, v2 ; encoding: [0x02,0x6b,0x02,0x7e]
// VI: v_sin_f32_e32 v1, v2 ; encoding: [0x02,0x53,0x02,0x7e]
v_sin_f32 v1, v2
// SICI: v_cos_f32_e32 v1, v2 ; encoding: [0x02,0x6d,0x02,0x7e]
// VI: v_cos_f32_e32 v1, v2 ; encoding: [0x02,0x55,0x02,0x7e]
v_cos_f32 v1, v2
// SICI: v_not_b32_e32 v1, v2 ; encoding: [0x02,0x6f,0x02,0x7e]
// VI: v_not_b32_e32 v1, v2 ; encoding: [0x02,0x57,0x02,0x7e]
v_not_b32_e32 v1, v2
// SICI: v_bfrev_b32_e32 v1, v2 ; encoding: [0x02,0x71,0x02,0x7e]
// VI: v_bfrev_b32_e32 v1, v2 ; encoding: [0x02,0x59,0x02,0x7e]
v_bfrev_b32_e32 v1, v2
// SICI: v_ffbh_u32_e32 v1, v2 ; encoding: [0x02,0x73,0x02,0x7e]
// VI: v_ffbh_u32_e32 v1, v2 ; encoding: [0x02,0x5b,0x02,0x7e]
v_ffbh_u32_e32 v1, v2
// SICI: v_ffbl_b32_e32 v1, v2 ; encoding: [0x02,0x75,0x02,0x7e]
// VI: v_ffbl_b32_e32 v1, v2 ; encoding: [0x02,0x5d,0x02,0x7e]
v_ffbl_b32_e32 v1, v2
// SICI: v_ffbh_i32_e32 v1, v2 ; encoding: [0x02,0x77,0x02,0x7e]
// VI: v_ffbh_i32_e32 v1, v2 ; encoding: [0x02,0x5f,0x02,0x7e]
v_ffbh_i32_e32 v1, v2
// SICI: v_frexp_exp_i32_f64_e32 v1, v[2:3] ; encoding: [0x02,0x79,0x02,0x7e]
// VI: v_frexp_exp_i32_f64_e32 v1, v[2:3] ; encoding: [0x02,0x61,0x02,0x7e]
v_frexp_exp_i32_f64_e32 v1, v[2:3]
// SICI: v_frexp_mant_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x7b,0x02,0x7e]
// VI: v_frexp_mant_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x63,0x02,0x7e]
v_frexp_mant_f64_e32 v[1:2], v[2:3]
// SICI: v_fract_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x7d,0x02,0x7e]
// VI: v_fract_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x65,0x02,0x7e]
v_fract_f64_e32 v[1:2], v[2:3]
// SICI: v_frexp_exp_i32_f32_e32 v1, v2 ; encoding: [0x02,0x7f,0x02,0x7e]
// VI: v_frexp_exp_i32_f32_e32 v1, v2 ; encoding: [0x02,0x67,0x02,0x7e]
v_frexp_exp_i32_f32_e32 v1, v2
// SICI: v_frexp_mant_f32_e32 v1, v2 ; encoding: [0x02,0x81,0x02,0x7e]
// VI: v_frexp_mant_f32_e32 v1, v2 ; encoding: [0x02,0x69,0x02,0x7e]
v_frexp_mant_f32 v1, v2
// SICI: v_clrexcp ; encoding: [0x00,0x82,0x00,0x7e]
// VI: v_clrexcp ; encoding: [0x00,0x6a,0x00,0x7e]
v_clrexcp_e32
// SICI: v_movreld_b32_e32 v1, v2 ; encoding: [0x02,0x85,0x02,0x7e]
// VI: v_movreld_b32_e32 v1, v2 ; encoding: [0x02,0x6d,0x02,0x7e]
v_movreld_b32_e32 v1, v2
// SICI: v_movrels_b32_e32 v1, v2 ; encoding: [0x02,0x87,0x02,0x7e]
// VI: v_movrels_b32_e32 v1, v2 ; encoding: [0x02,0x6f,0x02,0x7e]
v_movrels_b32_e32 v1, v2
// SICI: v_movrelsd_b32_e32 v1, v2 ; encoding: [0x02,0x89,0x02,0x7e]
// VI: v_movrelsd_b32_e32 v1, v2 ; encoding: [0x02,0x71,0x02,0x7e]
v_movrelsd_b32_e32 v1, v2
// NOSI: error: instruction not supported on this GPU
// NOSI: v_log_legacy_f32 v1, v2
// CI: v_log_legacy_f32_e32 v1, v2 ; encoding: [0x02,0x8b,0x02,0x7e]
// VI: v_log_legacy_f32_e32 v1, v2 ; encoding: [0x02,0x99,0x02,0x7e]
v_log_legacy_f32 v1, v2
// NOSI: error: instruction not supported on this GPU
// NOSI: v_exp_legacy_f32 v1, v2
// CI: v_exp_legacy_f32_e32 v1, v2 ; encoding: [0x02,0x8d,0x02,0x7e]
// VI: v_exp_legacy_f32_e32 v1, v2 ; encoding: [0x02,0x97,0x02,0x7e]
v_exp_legacy_f32 v1, v2
// NOSICI: error: instruction not supported on this GPU
// NOSICI: v_cvt_f16_u16_e32 v1, v2
// VI: v_cvt_f16_u16_e32 v1, v2 ; encoding: [0x02,0x73,0x02,0x7e]
v_cvt_f16_u16_e32 v1, v2
// NOSICI: error: instruction not supported on this GPU
// NOSICI: v_cvt_f16_i16_e32 v1, v2
// VI: v_cvt_f16_i16_e32 v1, v2 ; encoding: [0x02,0x75,0x02,0x7e]
v_cvt_f16_i16_e32 v1, v2
// NOSICI: error: instruction not supported on this GPU
// NOSICI: v_cvt_u16_f16_e32 v1, v2
// VI: v_cvt_u16_f16_e32 v1, v2 ; encoding: [0x02,0x77,0x02,0x7e]
v_cvt_u16_f16_e32 v1, v2
// NOSICI: error: instruction not supported on this GPU
// NOSICI: v_cvt_i16_f16_e32 v1, v2
// VI: v_cvt_i16_f16_e32 v1, v2 ; encoding: [0x02,0x79,0x02,0x7e]
v_cvt_i16_f16_e32 v1, v2
// NOSICI: error: instruction not supported on this GPU
// NOSICI: v_rcp_f16_e32 v1, v2
// VI: v_rcp_f16_e32 v1, v2 ; encoding: [0x02,0x7b,0x02,0x7e]
v_rcp_f16_e32 v1, v2
// NOSICI: error: instruction not supported on this GPU
// NOSICI: v_sqrt_f16_e32 v1, v2
// VI: v_sqrt_f16_e32 v1, v2 ; encoding: [0x02,0x7d,0x02,0x7e]
v_sqrt_f16_e32 v1, v2
// NOSICI: error: instruction not supported on this GPU
// NOSICI: v_rsq_f16_e32 v1, v2
// VI: v_rsq_f16_e32 v1, v2 ; encoding: [0x02,0x7f,0x02,0x7e]
v_rsq_f16_e32 v1, v2
// NOSICI: error: instruction not supported on this GPU
// NOSICI: v_log_f16_e32 v1, v2
// VI: v_log_f16_e32 v1, v2 ; encoding: [0x02,0x81,0x02,0x7e]
v_log_f16_e32 v1, v2
// NOSICI: error: instruction not supported on this GPU
// NOSICI: v_exp_f16_e32 v1, v2
// VI: v_exp_f16_e32 v1, v2 ; encoding: [0x02,0x83,0x02,0x7e]
v_exp_f16_e32 v1, v2
// NOSICI: error: instruction not supported on this GPU
// NOSICI: v_frexp_mant_f16_e32 v1, v2
// VI: v_frexp_mant_f16_e32 v1, v2 ; encoding: [0x02,0x85,0x02,0x7e]
v_frexp_mant_f16_e32 v1, v2
// NOSICI: error: instruction not supported on this GPU
// NOSICI: v_frexp_exp_i16_f16_e32 v1, v2
// VI: v_frexp_exp_i16_f16_e32 v1, v2 ; encoding: [0x02,0x87,0x02,0x7e]
v_frexp_exp_i16_f16_e32 v1, v2
// NOSICI: error: instruction not supported on this GPU
// NOSICI: v_floor_f16_e32 v1, v2
// VI: v_floor_f16_e32 v1, v2 ; encoding: [0x02,0x89,0x02,0x7e]
v_floor_f16_e32 v1, v2
// NOSICI: error: instruction not supported on this GPU
// NOSICI: v_ceil_f16_e32 v1, v2
// VI: v_ceil_f16_e32 v1, v2 ; encoding: [0x02,0x8b,0x02,0x7e]
v_ceil_f16_e32 v1, v2
// NOSICI: error: instruction not supported on this GPU
// NOSICI: v_trunc_f16_e32 v1, v2
// VI: v_trunc_f16_e32 v1, v2 ; encoding: [0x02,0x8d,0x02,0x7e]
v_trunc_f16_e32 v1, v2
// NOSICI: error: instruction not supported on this GPU
// NOSICI: v_rndne_f16_e32 v1, v2
// VI: v_rndne_f16_e32 v1, v2 ; encoding: [0x02,0x8f,0x02,0x7e]
v_rndne_f16_e32 v1, v2
// NOSICI: error: instruction not supported on this GPU
// NOSICI: v_fract_f16_e32 v1, v2
// VI: v_fract_f16_e32 v1, v2 ; encoding: [0x02,0x91,0x02,0x7e]
v_fract_f16_e32 v1, v2
// NOSICI: error: instruction not supported on this GPU
// NOSICI: v_sin_f16_e32 v1, v2
// VI: v_sin_f16_e32 v1, v2 ; encoding: [0x02,0x93,0x02,0x7e]
v_sin_f16_e32 v1, v2
// NOSICI: error: instruction not supported on this GPU
// NOSICI: v_cos_f16_e32 v1, v2
// VI: v_cos_f16_e32 v1, v2 ; encoding: [0x02,0x95,0x02,0x7e]
v_cos_f16_e32 v1, v2
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