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a84333d938
Summary: This patch makes progress on the 'unsigned -> Register' rewrite for `TargetInstrInfo::loadRegFromStack` and `TII::storeRegToStack`. Reviewers: arsenm, craig.topper, uweigand, jpienaar, atanasyan, venkatra, robertlytton, dylanmckay, t.p.northover, kparzysz, tstellar, k-ishizaka Reviewed By: arsenm Subscribers: wuzish, merge_guards_bot, jyknight, sdardis, nemanjai, jvesely, wdng, nhaehnle, hiraditya, kbarton, fedor.sergeev, asb, rbar, johnrusso, simoncook, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, Jim, lenary, s.egerton, pzheng, sameer.abuasal, apazos, luismarques, kerbowa, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D73870
131 lines
5.3 KiB
C++
131 lines
5.3 KiB
C++
//===- Mips16InstrInfo.h - Mips16 Instruction Information -------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Mips16 implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_MIPS_MIPS16INSTRINFO_H
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#define LLVM_LIB_TARGET_MIPS_MIPS16INSTRINFO_H
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#include "Mips16RegisterInfo.h"
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#include "MipsInstrInfo.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/Support/MathExtras.h"
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#include <cstdint>
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namespace llvm {
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class MCInstrDesc;
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class MipsSubtarget;
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class Mips16InstrInfo : public MipsInstrInfo {
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const Mips16RegisterInfo RI;
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public:
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explicit Mips16InstrInfo(const MipsSubtarget &STI);
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const MipsRegisterInfo &getRegisterInfo() const override;
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/// isLoadFromStackSlot - If the specified machine instruction is a direct
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/// load from a stack slot, return the virtual or physical register number of
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/// the destination along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than loading from the stack slot.
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unsigned isLoadFromStackSlot(const MachineInstr &MI,
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int &FrameIndex) const override;
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/// isStoreToStackSlot - If the specified machine instruction is a direct
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/// store to a stack slot, return the virtual or physical register number of
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/// the source reg along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than storing to the stack slot.
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unsigned isStoreToStackSlot(const MachineInstr &MI,
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int &FrameIndex) const override;
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void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
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const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
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bool KillSrc) const override;
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void storeRegToStack(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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Register SrcReg, bool isKill, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI,
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int64_t Offset) const override;
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void loadRegFromStack(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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Register DestReg, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI,
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int64_t Offset) const override;
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bool expandPostRAPseudo(MachineInstr &MI) const override;
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unsigned getOppositeBranchOpc(unsigned Opc) const override;
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// Adjust SP by FrameSize bytes. Save RA, S0, S1
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void makeFrame(unsigned SP, int64_t FrameSize, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const;
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// Adjust SP by FrameSize bytes. Restore RA, S0, S1
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void restoreFrame(unsigned SP, int64_t FrameSize, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const;
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/// Adjust SP by Amount bytes.
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void adjustStackPtr(unsigned SP, int64_t Amount, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const override;
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/// Emit a series of instructions to load an immediate.
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// This is to adjust some FrameReg. We return the new register to be used
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// in place of FrameReg and the adjusted immediate field (&NewImm)
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unsigned loadImmediate(unsigned FrameReg, int64_t Imm, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator II, const DebugLoc &DL,
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unsigned &NewImm) const;
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static bool validImmediate(unsigned Opcode, unsigned Reg, int64_t Amount);
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static bool validSpImm8(int offset) {
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return ((offset & 7) == 0) && isInt<11>(offset);
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}
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// build the proper one based on the Imm field
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const MCInstrDesc& AddiuSpImm(int64_t Imm) const;
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void BuildAddiuSpImm
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(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, int64_t Imm) const;
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protected:
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/// If the specific machine instruction is a instruction that moves/copies
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/// value from one register to another register return destination and source
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/// registers as machine operands.
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Optional<DestSourcePair> isCopyInstrImpl(const MachineInstr &MI) const override;
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private:
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unsigned getAnalyzableBrOpc(unsigned Opc) const override;
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void ExpandRetRA16(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned Opc) const;
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// Adjust SP by Amount bytes where bytes can be up to 32bit number.
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void adjustStackPtrBig(unsigned SP, int64_t Amount, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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unsigned Reg1, unsigned Reg2) const;
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// Adjust SP by Amount bytes where bytes can be up to 32bit number.
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void adjustStackPtrBigUnrestricted(unsigned SP, int64_t Amount,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const;
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};
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} // end namespace llvm
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#endif // LLVM_LIB_TARGET_MIPS_MIPS16INSTRINFO_H
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