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https://github.com/RPCS3/llvm-mirror.git
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7bd1807a26
Reviewers: efriedma, sdesmalen, c-rhodes, craig.topper Reviewed By: craig.topper Subscribers: tschuett, hiraditya, rkruppe, psnobl, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D80331
854 lines
33 KiB
C++
854 lines
33 KiB
C++
//===- X86InterleavedAccess.cpp -------------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// This file contains the X86 implementation of the interleaved accesses
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/// optimization generating X86-specific instructions/intrinsics for
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/// interleaved access groups.
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//
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//===----------------------------------------------------------------------===//
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#include "X86ISelLowering.h"
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#include "X86Subtarget.h"
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/Analysis/VectorUtils.h"
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#include "llvm/IR/Constants.h"
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#include "llvm/IR/DataLayout.h"
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#include "llvm/IR/DerivedTypes.h"
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#include "llvm/IR/IRBuilder.h"
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#include "llvm/IR/Instruction.h"
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#include "llvm/IR/Instructions.h"
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#include "llvm/IR/Module.h"
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#include "llvm/IR/Type.h"
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#include "llvm/IR/Value.h"
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#include "llvm/Support/Casting.h"
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#include "llvm/Support/MachineValueType.h"
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#include <algorithm>
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#include <cassert>
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#include <cmath>
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#include <cstdint>
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using namespace llvm;
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namespace {
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/// This class holds necessary information to represent an interleaved
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/// access group and supports utilities to lower the group into
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/// X86-specific instructions/intrinsics.
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/// E.g. A group of interleaving access loads (Factor = 2; accessing every
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/// other element)
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/// %wide.vec = load <8 x i32>, <8 x i32>* %ptr
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/// %v0 = shuffle <8 x i32> %wide.vec, <8 x i32> undef, <0, 2, 4, 6>
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/// %v1 = shuffle <8 x i32> %wide.vec, <8 x i32> undef, <1, 3, 5, 7>
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class X86InterleavedAccessGroup {
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/// Reference to the wide-load instruction of an interleaved access
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/// group.
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Instruction *const Inst;
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/// Reference to the shuffle(s), consumer(s) of the (load) 'Inst'.
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ArrayRef<ShuffleVectorInst *> Shuffles;
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/// Reference to the starting index of each user-shuffle.
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ArrayRef<unsigned> Indices;
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/// Reference to the interleaving stride in terms of elements.
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const unsigned Factor;
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/// Reference to the underlying target.
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const X86Subtarget &Subtarget;
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const DataLayout &DL;
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IRBuilder<> &Builder;
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/// Breaks down a vector \p 'Inst' of N elements into \p NumSubVectors
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/// sub vectors of type \p T. Returns the sub-vectors in \p DecomposedVectors.
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void decompose(Instruction *Inst, unsigned NumSubVectors, VectorType *T,
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SmallVectorImpl<Instruction *> &DecomposedVectors);
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/// Performs matrix transposition on a 4x4 matrix \p InputVectors and
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/// returns the transposed-vectors in \p TransposedVectors.
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/// E.g.
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/// InputVectors:
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/// In-V0 = p1, p2, p3, p4
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/// In-V1 = q1, q2, q3, q4
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/// In-V2 = r1, r2, r3, r4
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/// In-V3 = s1, s2, s3, s4
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/// OutputVectors:
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/// Out-V0 = p1, q1, r1, s1
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/// Out-V1 = p2, q2, r2, s2
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/// Out-V2 = p3, q3, r3, s3
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/// Out-V3 = P4, q4, r4, s4
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void transpose_4x4(ArrayRef<Instruction *> InputVectors,
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SmallVectorImpl<Value *> &TransposedMatrix);
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void interleave8bitStride4(ArrayRef<Instruction *> InputVectors,
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SmallVectorImpl<Value *> &TransposedMatrix,
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unsigned NumSubVecElems);
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void interleave8bitStride4VF8(ArrayRef<Instruction *> InputVectors,
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SmallVectorImpl<Value *> &TransposedMatrix);
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void interleave8bitStride3(ArrayRef<Instruction *> InputVectors,
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SmallVectorImpl<Value *> &TransposedMatrix,
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unsigned NumSubVecElems);
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void deinterleave8bitStride3(ArrayRef<Instruction *> InputVectors,
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SmallVectorImpl<Value *> &TransposedMatrix,
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unsigned NumSubVecElems);
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public:
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/// In order to form an interleaved access group X86InterleavedAccessGroup
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/// requires a wide-load instruction \p 'I', a group of interleaved-vectors
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/// \p Shuffs, reference to the first indices of each interleaved-vector
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/// \p 'Ind' and the interleaving stride factor \p F. In order to generate
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/// X86-specific instructions/intrinsics it also requires the underlying
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/// target information \p STarget.
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explicit X86InterleavedAccessGroup(Instruction *I,
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ArrayRef<ShuffleVectorInst *> Shuffs,
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ArrayRef<unsigned> Ind, const unsigned F,
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const X86Subtarget &STarget,
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IRBuilder<> &B)
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: Inst(I), Shuffles(Shuffs), Indices(Ind), Factor(F), Subtarget(STarget),
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DL(Inst->getModule()->getDataLayout()), Builder(B) {}
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/// Returns true if this interleaved access group can be lowered into
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/// x86-specific instructions/intrinsics, false otherwise.
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bool isSupported() const;
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/// Lowers this interleaved access group into X86-specific
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/// instructions/intrinsics.
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bool lowerIntoOptimizedSequence();
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};
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} // end anonymous namespace
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bool X86InterleavedAccessGroup::isSupported() const {
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VectorType *ShuffleVecTy = Shuffles[0]->getType();
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Type *ShuffleEltTy = ShuffleVecTy->getElementType();
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unsigned ShuffleElemSize = DL.getTypeSizeInBits(ShuffleEltTy);
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unsigned WideInstSize;
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// Currently, lowering is supported for the following vectors:
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// Stride 4:
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// 1. Store and load of 4-element vectors of 64 bits on AVX.
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// 2. Store of 16/32-element vectors of 8 bits on AVX.
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// Stride 3:
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// 1. Load of 16/32-element vectors of 8 bits on AVX.
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if (!Subtarget.hasAVX() || (Factor != 4 && Factor != 3))
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return false;
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if (isa<LoadInst>(Inst)) {
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WideInstSize = DL.getTypeSizeInBits(Inst->getType());
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if (cast<LoadInst>(Inst)->getPointerAddressSpace())
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return false;
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} else
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WideInstSize = DL.getTypeSizeInBits(Shuffles[0]->getType());
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// We support shuffle represents stride 4 for byte type with size of
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// WideInstSize.
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if (ShuffleElemSize == 64 && WideInstSize == 1024 && Factor == 4)
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return true;
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if (ShuffleElemSize == 8 && isa<StoreInst>(Inst) && Factor == 4 &&
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(WideInstSize == 256 || WideInstSize == 512 || WideInstSize == 1024 ||
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WideInstSize == 2048))
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return true;
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if (ShuffleElemSize == 8 && Factor == 3 &&
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(WideInstSize == 384 || WideInstSize == 768 || WideInstSize == 1536))
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return true;
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return false;
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}
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void X86InterleavedAccessGroup::decompose(
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Instruction *VecInst, unsigned NumSubVectors, VectorType *SubVecTy,
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SmallVectorImpl<Instruction *> &DecomposedVectors) {
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assert((isa<LoadInst>(VecInst) || isa<ShuffleVectorInst>(VecInst)) &&
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"Expected Load or Shuffle");
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Type *VecWidth = VecInst->getType();
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(void)VecWidth;
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assert(VecWidth->isVectorTy() &&
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DL.getTypeSizeInBits(VecWidth) >=
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DL.getTypeSizeInBits(SubVecTy) * NumSubVectors &&
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"Invalid Inst-size!!!");
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if (auto *SVI = dyn_cast<ShuffleVectorInst>(VecInst)) {
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Value *Op0 = SVI->getOperand(0);
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Value *Op1 = SVI->getOperand(1);
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// Generate N(= NumSubVectors) shuffles of T(= SubVecTy) type.
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for (unsigned i = 0; i < NumSubVectors; ++i)
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DecomposedVectors.push_back(
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cast<ShuffleVectorInst>(Builder.CreateShuffleVector(
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Op0, Op1,
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createSequentialMask(Indices[i], SubVecTy->getNumElements(),
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0))));
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return;
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}
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// Decompose the load instruction.
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LoadInst *LI = cast<LoadInst>(VecInst);
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Type *VecBaseTy, *VecBasePtrTy;
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Value *VecBasePtr;
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unsigned int NumLoads = NumSubVectors;
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// In the case of stride 3 with a vector of 32 elements load the information
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// in the following way:
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// [0,1...,VF/2-1,VF/2+VF,VF/2+VF+1,...,2VF-1]
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unsigned VecLength = DL.getTypeSizeInBits(VecWidth);
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if (VecLength == 768 || VecLength == 1536) {
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VecBaseTy = FixedVectorType::get(Type::getInt8Ty(LI->getContext()), 16);
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VecBasePtrTy = VecBaseTy->getPointerTo(LI->getPointerAddressSpace());
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VecBasePtr = Builder.CreateBitCast(LI->getPointerOperand(), VecBasePtrTy);
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NumLoads = NumSubVectors * (VecLength / 384);
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} else {
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VecBaseTy = SubVecTy;
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VecBasePtrTy = VecBaseTy->getPointerTo(LI->getPointerAddressSpace());
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VecBasePtr = Builder.CreateBitCast(LI->getPointerOperand(), VecBasePtrTy);
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}
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// Generate N loads of T type.
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assert(VecBaseTy->getPrimitiveSizeInBits().isByteSized() &&
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"VecBaseTy's size must be a multiple of 8");
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const Align FirstAlignment = LI->getAlign();
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const Align SubsequentAlignment = commonAlignment(
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FirstAlignment, VecBaseTy->getPrimitiveSizeInBits().getFixedSize() / 8);
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Align Alignment = FirstAlignment;
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for (unsigned i = 0; i < NumLoads; i++) {
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// TODO: Support inbounds GEP.
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Value *NewBasePtr =
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Builder.CreateGEP(VecBaseTy, VecBasePtr, Builder.getInt32(i));
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Instruction *NewLoad =
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Builder.CreateAlignedLoad(VecBaseTy, NewBasePtr, Alignment);
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DecomposedVectors.push_back(NewLoad);
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Alignment = SubsequentAlignment;
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}
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}
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// Changing the scale of the vector type by reducing the number of elements and
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// doubling the scalar size.
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static MVT scaleVectorType(MVT VT) {
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unsigned ScalarSize = VT.getVectorElementType().getScalarSizeInBits() * 2;
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return MVT::getVectorVT(MVT::getIntegerVT(ScalarSize),
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VT.getVectorNumElements() / 2);
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}
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static constexpr int Concat[] = {
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0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
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16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
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32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
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48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63};
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// genShuffleBland - Creates shuffle according to two vectors.This function is
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// only works on instructions with lane inside 256 registers. According to
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// the mask 'Mask' creates a new Mask 'Out' by the offset of the mask. The
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// offset amount depends on the two integer, 'LowOffset' and 'HighOffset'.
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// Where the 'LowOffset' refers to the first vector and the highOffset refers to
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// the second vector.
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// |a0....a5,b0....b4,c0....c4|a16..a21,b16..b20,c16..c20|
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// |c5...c10,a5....a9,b5....b9|c21..c26,a22..a26,b21..b25|
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// |b10..b15,c11..c15,a10..a15|b26..b31,c27..c31,a27..a31|
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// For the sequence to work as a mirror to the load.
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// We must consider the elements order as above.
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// In this function we are combining two types of shuffles.
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// The first one is vpshufed and the second is a type of "blend" shuffle.
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// By computing the shuffle on a sequence of 16 elements(one lane) and add the
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// correct offset. We are creating a vpsuffed + blend sequence between two
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// shuffles.
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static void genShuffleBland(MVT VT, ArrayRef<int> Mask,
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SmallVectorImpl<int> &Out, int LowOffset,
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int HighOffset) {
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assert(VT.getSizeInBits() >= 256 &&
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"This function doesn't accept width smaller then 256");
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unsigned NumOfElm = VT.getVectorNumElements();
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for (unsigned i = 0; i < Mask.size(); i++)
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Out.push_back(Mask[i] + LowOffset);
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for (unsigned i = 0; i < Mask.size(); i++)
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Out.push_back(Mask[i] + HighOffset + NumOfElm);
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}
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// reorderSubVector returns the data to is the original state. And de-facto is
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// the opposite of the function concatSubVector.
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// For VecElems = 16
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// Invec[0] - |0| TransposedMatrix[0] - |0|
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// Invec[1] - |1| => TransposedMatrix[1] - |1|
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// Invec[2] - |2| TransposedMatrix[2] - |2|
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// For VecElems = 32
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// Invec[0] - |0|3| TransposedMatrix[0] - |0|1|
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// Invec[1] - |1|4| => TransposedMatrix[1] - |2|3|
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// Invec[2] - |2|5| TransposedMatrix[2] - |4|5|
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// For VecElems = 64
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// Invec[0] - |0|3|6|9 | TransposedMatrix[0] - |0|1|2 |3 |
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// Invec[1] - |1|4|7|10| => TransposedMatrix[1] - |4|5|6 |7 |
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// Invec[2] - |2|5|8|11| TransposedMatrix[2] - |8|9|10|11|
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static void reorderSubVector(MVT VT, SmallVectorImpl<Value *> &TransposedMatrix,
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ArrayRef<Value *> Vec, ArrayRef<int> VPShuf,
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unsigned VecElems, unsigned Stride,
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IRBuilder<> &Builder) {
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if (VecElems == 16) {
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for (unsigned i = 0; i < Stride; i++)
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TransposedMatrix[i] = Builder.CreateShuffleVector(
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Vec[i], UndefValue::get(Vec[i]->getType()), VPShuf);
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return;
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}
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SmallVector<int, 32> OptimizeShuf;
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Value *Temp[8];
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for (unsigned i = 0; i < (VecElems / 16) * Stride; i += 2) {
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genShuffleBland(VT, VPShuf, OptimizeShuf, (i / Stride) * 16,
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(i + 1) / Stride * 16);
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Temp[i / 2] = Builder.CreateShuffleVector(
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Vec[i % Stride], Vec[(i + 1) % Stride], OptimizeShuf);
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OptimizeShuf.clear();
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}
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if (VecElems == 32) {
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std::copy(Temp, Temp + Stride, TransposedMatrix.begin());
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return;
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} else
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for (unsigned i = 0; i < Stride; i++)
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TransposedMatrix[i] =
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Builder.CreateShuffleVector(Temp[2 * i], Temp[2 * i + 1], Concat);
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}
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void X86InterleavedAccessGroup::interleave8bitStride4VF8(
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ArrayRef<Instruction *> Matrix,
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SmallVectorImpl<Value *> &TransposedMatrix) {
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// Assuming we start from the following vectors:
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// Matrix[0]= c0 c1 c2 c3 c4 ... c7
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// Matrix[1]= m0 m1 m2 m3 m4 ... m7
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// Matrix[2]= y0 y1 y2 y3 y4 ... y7
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// Matrix[3]= k0 k1 k2 k3 k4 ... k7
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MVT VT = MVT::v8i16;
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TransposedMatrix.resize(2);
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SmallVector<int, 16> MaskLow;
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SmallVector<int, 32> MaskLowTemp1, MaskLowWord;
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SmallVector<int, 32> MaskHighTemp1, MaskHighWord;
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for (unsigned i = 0; i < 8; ++i) {
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MaskLow.push_back(i);
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MaskLow.push_back(i + 8);
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}
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createUnpackShuffleMask(VT, MaskLowTemp1, true, false);
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createUnpackShuffleMask(VT, MaskHighTemp1, false, false);
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narrowShuffleMaskElts(2, MaskHighTemp1, MaskHighWord);
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narrowShuffleMaskElts(2, MaskLowTemp1, MaskLowWord);
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// IntrVec1Low = c0 m0 c1 m1 c2 m2 c3 m3 c4 m4 c5 m5 c6 m6 c7 m7
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// IntrVec2Low = y0 k0 y1 k1 y2 k2 y3 k3 y4 k4 y5 k5 y6 k6 y7 k7
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Value *IntrVec1Low =
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Builder.CreateShuffleVector(Matrix[0], Matrix[1], MaskLow);
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Value *IntrVec2Low =
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Builder.CreateShuffleVector(Matrix[2], Matrix[3], MaskLow);
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// TransposedMatrix[0] = c0 m0 y0 k0 c1 m1 y1 k1 c2 m2 y2 k2 c3 m3 y3 k3
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// TransposedMatrix[1] = c4 m4 y4 k4 c5 m5 y5 k5 c6 m6 y6 k6 c7 m7 y7 k7
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TransposedMatrix[0] =
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Builder.CreateShuffleVector(IntrVec1Low, IntrVec2Low, MaskLowWord);
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TransposedMatrix[1] =
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Builder.CreateShuffleVector(IntrVec1Low, IntrVec2Low, MaskHighWord);
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}
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void X86InterleavedAccessGroup::interleave8bitStride4(
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ArrayRef<Instruction *> Matrix, SmallVectorImpl<Value *> &TransposedMatrix,
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unsigned NumOfElm) {
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// Example: Assuming we start from the following vectors:
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// Matrix[0]= c0 c1 c2 c3 c4 ... c31
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// Matrix[1]= m0 m1 m2 m3 m4 ... m31
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// Matrix[2]= y0 y1 y2 y3 y4 ... y31
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// Matrix[3]= k0 k1 k2 k3 k4 ... k31
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MVT VT = MVT::getVectorVT(MVT::i8, NumOfElm);
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MVT HalfVT = scaleVectorType(VT);
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TransposedMatrix.resize(4);
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SmallVector<int, 32> MaskHigh;
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SmallVector<int, 32> MaskLow;
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SmallVector<int, 32> LowHighMask[2];
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SmallVector<int, 32> MaskHighTemp;
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SmallVector<int, 32> MaskLowTemp;
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// MaskHighTemp and MaskLowTemp built in the vpunpckhbw and vpunpcklbw X86
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// shuffle pattern.
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createUnpackShuffleMask(VT, MaskLow, true, false);
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createUnpackShuffleMask(VT, MaskHigh, false, false);
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// MaskHighTemp1 and MaskLowTemp1 built in the vpunpckhdw and vpunpckldw X86
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// shuffle pattern.
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createUnpackShuffleMask(HalfVT, MaskLowTemp, true, false);
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createUnpackShuffleMask(HalfVT, MaskHighTemp, false, false);
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narrowShuffleMaskElts(2, MaskLowTemp, LowHighMask[0]);
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narrowShuffleMaskElts(2, MaskHighTemp, LowHighMask[1]);
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// IntrVec1Low = c0 m0 c1 m1 ... c7 m7 | c16 m16 c17 m17 ... c23 m23
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// IntrVec1High = c8 m8 c9 m9 ... c15 m15 | c24 m24 c25 m25 ... c31 m31
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// IntrVec2Low = y0 k0 y1 k1 ... y7 k7 | y16 k16 y17 k17 ... y23 k23
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// IntrVec2High = y8 k8 y9 k9 ... y15 k15 | y24 k24 y25 k25 ... y31 k31
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Value *IntrVec[4];
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IntrVec[0] = Builder.CreateShuffleVector(Matrix[0], Matrix[1], MaskLow);
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IntrVec[1] = Builder.CreateShuffleVector(Matrix[0], Matrix[1], MaskHigh);
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IntrVec[2] = Builder.CreateShuffleVector(Matrix[2], Matrix[3], MaskLow);
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IntrVec[3] = Builder.CreateShuffleVector(Matrix[2], Matrix[3], MaskHigh);
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|
|
// cmyk4 cmyk5 cmyk6 cmyk7 | cmyk20 cmyk21 cmyk22 cmyk23
|
|
// cmyk12 cmyk13 cmyk14 cmyk15 | cmyk28 cmyk29 cmyk30 cmyk31
|
|
// cmyk0 cmyk1 cmyk2 cmyk3 | cmyk16 cmyk17 cmyk18 cmyk19
|
|
// cmyk8 cmyk9 cmyk10 cmyk11 | cmyk24 cmyk25 cmyk26 cmyk27
|
|
|
|
Value *VecOut[4];
|
|
for (int i = 0; i < 4; i++)
|
|
VecOut[i] = Builder.CreateShuffleVector(IntrVec[i / 2], IntrVec[i / 2 + 2],
|
|
LowHighMask[i % 2]);
|
|
|
|
// cmyk0 cmyk1 cmyk2 cmyk3 | cmyk4 cmyk5 cmyk6 cmyk7
|
|
// cmyk8 cmyk9 cmyk10 cmyk11 | cmyk12 cmyk13 cmyk14 cmyk15
|
|
// cmyk16 cmyk17 cmyk18 cmyk19 | cmyk20 cmyk21 cmyk22 cmyk23
|
|
// cmyk24 cmyk25 cmyk26 cmyk27 | cmyk28 cmyk29 cmyk30 cmyk31
|
|
|
|
if (VT == MVT::v16i8) {
|
|
std::copy(VecOut, VecOut + 4, TransposedMatrix.begin());
|
|
return;
|
|
}
|
|
|
|
reorderSubVector(VT, TransposedMatrix, VecOut, makeArrayRef(Concat, 16),
|
|
NumOfElm, 4, Builder);
|
|
}
|
|
|
|
// createShuffleStride returns shuffle mask of size N.
|
|
// The shuffle pattern is as following :
|
|
// {0, Stride%(VF/Lane), (2*Stride%(VF/Lane))...(VF*Stride/Lane)%(VF/Lane),
|
|
// (VF/ Lane) ,(VF / Lane)+Stride%(VF/Lane),...,
|
|
// (VF / Lane)+(VF*Stride/Lane)%(VF/Lane)}
|
|
// Where Lane is the # of lanes in a register:
|
|
// VectorSize = 128 => Lane = 1
|
|
// VectorSize = 256 => Lane = 2
|
|
// For example shuffle pattern for VF 16 register size 256 -> lanes = 2
|
|
// {<[0|3|6|1|4|7|2|5]-[8|11|14|9|12|15|10|13]>}
|
|
static void createShuffleStride(MVT VT, int Stride,
|
|
SmallVectorImpl<int> &Mask) {
|
|
int VectorSize = VT.getSizeInBits();
|
|
int VF = VT.getVectorNumElements();
|
|
int LaneCount = std::max(VectorSize / 128, 1);
|
|
for (int Lane = 0; Lane < LaneCount; Lane++)
|
|
for (int i = 0, LaneSize = VF / LaneCount; i != LaneSize; ++i)
|
|
Mask.push_back((i * Stride) % LaneSize + LaneSize * Lane);
|
|
}
|
|
|
|
// setGroupSize sets 'SizeInfo' to the size(number of elements) of group
|
|
// inside mask a shuffleMask. A mask contains exactly 3 groups, where
|
|
// each group is a monotonically increasing sequence with stride 3.
|
|
// For example shuffleMask {0,3,6,1,4,7,2,5} => {3,3,2}
|
|
static void setGroupSize(MVT VT, SmallVectorImpl<int> &SizeInfo) {
|
|
int VectorSize = VT.getSizeInBits();
|
|
int VF = VT.getVectorNumElements() / std::max(VectorSize / 128, 1);
|
|
for (int i = 0, FirstGroupElement = 0; i < 3; i++) {
|
|
int GroupSize = std::ceil((VF - FirstGroupElement) / 3.0);
|
|
SizeInfo.push_back(GroupSize);
|
|
FirstGroupElement = ((GroupSize)*3 + FirstGroupElement) % VF;
|
|
}
|
|
}
|
|
|
|
// DecodePALIGNRMask returns the shuffle mask of vpalign instruction.
|
|
// vpalign works according to lanes
|
|
// Where Lane is the # of lanes in a register:
|
|
// VectorWide = 128 => Lane = 1
|
|
// VectorWide = 256 => Lane = 2
|
|
// For Lane = 1 shuffle pattern is: {DiffToJump,...,DiffToJump+VF-1}.
|
|
// For Lane = 2 shuffle pattern is:
|
|
// {DiffToJump,...,VF/2-1,VF,...,DiffToJump+VF-1}.
|
|
// Imm variable sets the offset amount. The result of the
|
|
// function is stored inside ShuffleMask vector and it built as described in
|
|
// the begin of the description. AlignDirection is a boolean that indicates the
|
|
// direction of the alignment. (false - align to the "right" side while true -
|
|
// align to the "left" side)
|
|
static void DecodePALIGNRMask(MVT VT, unsigned Imm,
|
|
SmallVectorImpl<int> &ShuffleMask,
|
|
bool AlignDirection = true, bool Unary = false) {
|
|
unsigned NumElts = VT.getVectorNumElements();
|
|
unsigned NumLanes = std::max((int)VT.getSizeInBits() / 128, 1);
|
|
unsigned NumLaneElts = NumElts / NumLanes;
|
|
|
|
Imm = AlignDirection ? Imm : (NumLaneElts - Imm);
|
|
unsigned Offset = Imm * (VT.getScalarSizeInBits() / 8);
|
|
|
|
for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
|
|
for (unsigned i = 0; i != NumLaneElts; ++i) {
|
|
unsigned Base = i + Offset;
|
|
// if i+offset is out of this lane then we actually need the other source
|
|
// If Unary the other source is the first source.
|
|
if (Base >= NumLaneElts)
|
|
Base = Unary ? Base % NumLaneElts : Base + NumElts - NumLaneElts;
|
|
ShuffleMask.push_back(Base + l);
|
|
}
|
|
}
|
|
}
|
|
|
|
// concatSubVector - The function rebuilds the data to a correct expected
|
|
// order. An assumption(The shape of the matrix) was taken for the
|
|
// deinterleaved to work with lane's instructions like 'vpalign' or 'vphuf'.
|
|
// This function ensures that the data is built in correct way for the lane
|
|
// instructions. Each lane inside the vector is a 128-bit length.
|
|
//
|
|
// The 'InVec' argument contains the data in increasing order. In InVec[0] You
|
|
// can find the first 128 bit data. The number of different lanes inside a
|
|
// vector depends on the 'VecElems'.In general, the formula is
|
|
// VecElems * type / 128. The size of the array 'InVec' depends and equal to
|
|
// 'VecElems'.
|
|
|
|
// For VecElems = 16
|
|
// Invec[0] - |0| Vec[0] - |0|
|
|
// Invec[1] - |1| => Vec[1] - |1|
|
|
// Invec[2] - |2| Vec[2] - |2|
|
|
|
|
// For VecElems = 32
|
|
// Invec[0] - |0|1| Vec[0] - |0|3|
|
|
// Invec[1] - |2|3| => Vec[1] - |1|4|
|
|
// Invec[2] - |4|5| Vec[2] - |2|5|
|
|
|
|
// For VecElems = 64
|
|
// Invec[0] - |0|1|2 |3 | Vec[0] - |0|3|6|9 |
|
|
// Invec[1] - |4|5|6 |7 | => Vec[1] - |1|4|7|10|
|
|
// Invec[2] - |8|9|10|11| Vec[2] - |2|5|8|11|
|
|
|
|
static void concatSubVector(Value **Vec, ArrayRef<Instruction *> InVec,
|
|
unsigned VecElems, IRBuilder<> &Builder) {
|
|
if (VecElems == 16) {
|
|
for (int i = 0; i < 3; i++)
|
|
Vec[i] = InVec[i];
|
|
return;
|
|
}
|
|
|
|
for (unsigned j = 0; j < VecElems / 32; j++)
|
|
for (int i = 0; i < 3; i++)
|
|
Vec[i + j * 3] = Builder.CreateShuffleVector(
|
|
InVec[j * 6 + i], InVec[j * 6 + i + 3], makeArrayRef(Concat, 32));
|
|
|
|
if (VecElems == 32)
|
|
return;
|
|
|
|
for (int i = 0; i < 3; i++)
|
|
Vec[i] = Builder.CreateShuffleVector(Vec[i], Vec[i + 3], Concat);
|
|
}
|
|
|
|
void X86InterleavedAccessGroup::deinterleave8bitStride3(
|
|
ArrayRef<Instruction *> InVec, SmallVectorImpl<Value *> &TransposedMatrix,
|
|
unsigned VecElems) {
|
|
// Example: Assuming we start from the following vectors:
|
|
// Matrix[0]= a0 b0 c0 a1 b1 c1 a2 b2
|
|
// Matrix[1]= c2 a3 b3 c3 a4 b4 c4 a5
|
|
// Matrix[2]= b5 c5 a6 b6 c6 a7 b7 c7
|
|
|
|
TransposedMatrix.resize(3);
|
|
SmallVector<int, 32> VPShuf;
|
|
SmallVector<int, 32> VPAlign[2];
|
|
SmallVector<int, 32> VPAlign2;
|
|
SmallVector<int, 32> VPAlign3;
|
|
SmallVector<int, 3> GroupSize;
|
|
Value *Vec[6], *TempVector[3];
|
|
|
|
MVT VT = MVT::getVT(Shuffles[0]->getType());
|
|
|
|
createShuffleStride(VT, 3, VPShuf);
|
|
setGroupSize(VT, GroupSize);
|
|
|
|
for (int i = 0; i < 2; i++)
|
|
DecodePALIGNRMask(VT, GroupSize[2 - i], VPAlign[i], false);
|
|
|
|
DecodePALIGNRMask(VT, GroupSize[2] + GroupSize[1], VPAlign2, true, true);
|
|
DecodePALIGNRMask(VT, GroupSize[1], VPAlign3, true, true);
|
|
|
|
concatSubVector(Vec, InVec, VecElems, Builder);
|
|
// Vec[0]= a0 a1 a2 b0 b1 b2 c0 c1
|
|
// Vec[1]= c2 c3 c4 a3 a4 a5 b3 b4
|
|
// Vec[2]= b5 b6 b7 c5 c6 c7 a6 a7
|
|
|
|
for (int i = 0; i < 3; i++)
|
|
Vec[i] = Builder.CreateShuffleVector(
|
|
Vec[i], UndefValue::get(Vec[0]->getType()), VPShuf);
|
|
|
|
// TempVector[0]= a6 a7 a0 a1 a2 b0 b1 b2
|
|
// TempVector[1]= c0 c1 c2 c3 c4 a3 a4 a5
|
|
// TempVector[2]= b3 b4 b5 b6 b7 c5 c6 c7
|
|
|
|
for (int i = 0; i < 3; i++)
|
|
TempVector[i] =
|
|
Builder.CreateShuffleVector(Vec[(i + 2) % 3], Vec[i], VPAlign[0]);
|
|
|
|
// Vec[0]= a3 a4 a5 a6 a7 a0 a1 a2
|
|
// Vec[1]= c5 c6 c7 c0 c1 c2 c3 c4
|
|
// Vec[2]= b0 b1 b2 b3 b4 b5 b6 b7
|
|
|
|
for (int i = 0; i < 3; i++)
|
|
Vec[i] = Builder.CreateShuffleVector(TempVector[(i + 1) % 3], TempVector[i],
|
|
VPAlign[1]);
|
|
|
|
// TransposedMatrix[0]= a0 a1 a2 a3 a4 a5 a6 a7
|
|
// TransposedMatrix[1]= b0 b1 b2 b3 b4 b5 b6 b7
|
|
// TransposedMatrix[2]= c0 c1 c2 c3 c4 c5 c6 c7
|
|
|
|
Value *TempVec = Builder.CreateShuffleVector(
|
|
Vec[1], UndefValue::get(Vec[1]->getType()), VPAlign3);
|
|
TransposedMatrix[0] = Builder.CreateShuffleVector(
|
|
Vec[0], UndefValue::get(Vec[1]->getType()), VPAlign2);
|
|
TransposedMatrix[1] = VecElems == 8 ? Vec[2] : TempVec;
|
|
TransposedMatrix[2] = VecElems == 8 ? TempVec : Vec[2];
|
|
}
|
|
|
|
// group2Shuffle reorder the shuffle stride back into continuous order.
|
|
// For example For VF16 with Mask1 = {0,3,6,9,12,15,2,5,8,11,14,1,4,7,10,13} =>
|
|
// MaskResult = {0,11,6,1,12,7,2,13,8,3,14,9,4,15,10,5}.
|
|
static void group2Shuffle(MVT VT, SmallVectorImpl<int> &Mask,
|
|
SmallVectorImpl<int> &Output) {
|
|
int IndexGroup[3] = {0, 0, 0};
|
|
int Index = 0;
|
|
int VectorWidth = VT.getSizeInBits();
|
|
int VF = VT.getVectorNumElements();
|
|
// Find the index of the different groups.
|
|
int Lane = (VectorWidth / 128 > 0) ? VectorWidth / 128 : 1;
|
|
for (int i = 0; i < 3; i++) {
|
|
IndexGroup[(Index * 3) % (VF / Lane)] = Index;
|
|
Index += Mask[i];
|
|
}
|
|
// According to the index compute the convert mask.
|
|
for (int i = 0; i < VF / Lane; i++) {
|
|
Output.push_back(IndexGroup[i % 3]);
|
|
IndexGroup[i % 3]++;
|
|
}
|
|
}
|
|
|
|
void X86InterleavedAccessGroup::interleave8bitStride3(
|
|
ArrayRef<Instruction *> InVec, SmallVectorImpl<Value *> &TransposedMatrix,
|
|
unsigned VecElems) {
|
|
// Example: Assuming we start from the following vectors:
|
|
// Matrix[0]= a0 a1 a2 a3 a4 a5 a6 a7
|
|
// Matrix[1]= b0 b1 b2 b3 b4 b5 b6 b7
|
|
// Matrix[2]= c0 c1 c2 c3 c3 a7 b7 c7
|
|
|
|
TransposedMatrix.resize(3);
|
|
SmallVector<int, 3> GroupSize;
|
|
SmallVector<int, 32> VPShuf;
|
|
SmallVector<int, 32> VPAlign[3];
|
|
SmallVector<int, 32> VPAlign2;
|
|
SmallVector<int, 32> VPAlign3;
|
|
|
|
Value *Vec[3], *TempVector[3];
|
|
MVT VT = MVT::getVectorVT(MVT::i8, VecElems);
|
|
|
|
setGroupSize(VT, GroupSize);
|
|
|
|
for (int i = 0; i < 3; i++)
|
|
DecodePALIGNRMask(VT, GroupSize[i], VPAlign[i]);
|
|
|
|
DecodePALIGNRMask(VT, GroupSize[1] + GroupSize[2], VPAlign2, false, true);
|
|
DecodePALIGNRMask(VT, GroupSize[1], VPAlign3, false, true);
|
|
|
|
// Vec[0]= a3 a4 a5 a6 a7 a0 a1 a2
|
|
// Vec[1]= c5 c6 c7 c0 c1 c2 c3 c4
|
|
// Vec[2]= b0 b1 b2 b3 b4 b5 b6 b7
|
|
|
|
Vec[0] = Builder.CreateShuffleVector(
|
|
InVec[0], UndefValue::get(InVec[0]->getType()), VPAlign2);
|
|
Vec[1] = Builder.CreateShuffleVector(
|
|
InVec[1], UndefValue::get(InVec[1]->getType()), VPAlign3);
|
|
Vec[2] = InVec[2];
|
|
|
|
// Vec[0]= a6 a7 a0 a1 a2 b0 b1 b2
|
|
// Vec[1]= c0 c1 c2 c3 c4 a3 a4 a5
|
|
// Vec[2]= b3 b4 b5 b6 b7 c5 c6 c7
|
|
|
|
for (int i = 0; i < 3; i++)
|
|
TempVector[i] =
|
|
Builder.CreateShuffleVector(Vec[i], Vec[(i + 2) % 3], VPAlign[1]);
|
|
|
|
// Vec[0]= a0 a1 a2 b0 b1 b2 c0 c1
|
|
// Vec[1]= c2 c3 c4 a3 a4 a5 b3 b4
|
|
// Vec[2]= b5 b6 b7 c5 c6 c7 a6 a7
|
|
|
|
for (int i = 0; i < 3; i++)
|
|
Vec[i] = Builder.CreateShuffleVector(TempVector[i], TempVector[(i + 1) % 3],
|
|
VPAlign[2]);
|
|
|
|
// TransposedMatrix[0] = a0 b0 c0 a1 b1 c1 a2 b2
|
|
// TransposedMatrix[1] = c2 a3 b3 c3 a4 b4 c4 a5
|
|
// TransposedMatrix[2] = b5 c5 a6 b6 c6 a7 b7 c7
|
|
|
|
unsigned NumOfElm = VT.getVectorNumElements();
|
|
group2Shuffle(VT, GroupSize, VPShuf);
|
|
reorderSubVector(VT, TransposedMatrix, Vec, VPShuf, NumOfElm, 3, Builder);
|
|
}
|
|
|
|
void X86InterleavedAccessGroup::transpose_4x4(
|
|
ArrayRef<Instruction *> Matrix,
|
|
SmallVectorImpl<Value *> &TransposedMatrix) {
|
|
assert(Matrix.size() == 4 && "Invalid matrix size");
|
|
TransposedMatrix.resize(4);
|
|
|
|
// dst = src1[0,1],src2[0,1]
|
|
static constexpr int IntMask1[] = {0, 1, 4, 5};
|
|
ArrayRef<int> Mask = makeArrayRef(IntMask1, 4);
|
|
Value *IntrVec1 = Builder.CreateShuffleVector(Matrix[0], Matrix[2], Mask);
|
|
Value *IntrVec2 = Builder.CreateShuffleVector(Matrix[1], Matrix[3], Mask);
|
|
|
|
// dst = src1[2,3],src2[2,3]
|
|
static constexpr int IntMask2[] = {2, 3, 6, 7};
|
|
Mask = makeArrayRef(IntMask2, 4);
|
|
Value *IntrVec3 = Builder.CreateShuffleVector(Matrix[0], Matrix[2], Mask);
|
|
Value *IntrVec4 = Builder.CreateShuffleVector(Matrix[1], Matrix[3], Mask);
|
|
|
|
// dst = src1[0],src2[0],src1[2],src2[2]
|
|
static constexpr int IntMask3[] = {0, 4, 2, 6};
|
|
Mask = makeArrayRef(IntMask3, 4);
|
|
TransposedMatrix[0] = Builder.CreateShuffleVector(IntrVec1, IntrVec2, Mask);
|
|
TransposedMatrix[2] = Builder.CreateShuffleVector(IntrVec3, IntrVec4, Mask);
|
|
|
|
// dst = src1[1],src2[1],src1[3],src2[3]
|
|
static constexpr int IntMask4[] = {1, 5, 3, 7};
|
|
Mask = makeArrayRef(IntMask4, 4);
|
|
TransposedMatrix[1] = Builder.CreateShuffleVector(IntrVec1, IntrVec2, Mask);
|
|
TransposedMatrix[3] = Builder.CreateShuffleVector(IntrVec3, IntrVec4, Mask);
|
|
}
|
|
|
|
// Lowers this interleaved access group into X86-specific
|
|
// instructions/intrinsics.
|
|
bool X86InterleavedAccessGroup::lowerIntoOptimizedSequence() {
|
|
SmallVector<Instruction *, 4> DecomposedVectors;
|
|
SmallVector<Value *, 4> TransposedVectors;
|
|
VectorType *ShuffleTy = Shuffles[0]->getType();
|
|
|
|
if (isa<LoadInst>(Inst)) {
|
|
// Try to generate target-sized register(/instruction).
|
|
decompose(Inst, Factor, ShuffleTy, DecomposedVectors);
|
|
|
|
auto *ShuffleEltTy = cast<VectorType>(Inst->getType());
|
|
unsigned NumSubVecElems = ShuffleEltTy->getNumElements() / Factor;
|
|
// Perform matrix-transposition in order to compute interleaved
|
|
// results by generating some sort of (optimized) target-specific
|
|
// instructions.
|
|
|
|
switch (NumSubVecElems) {
|
|
default:
|
|
return false;
|
|
case 4:
|
|
transpose_4x4(DecomposedVectors, TransposedVectors);
|
|
break;
|
|
case 8:
|
|
case 16:
|
|
case 32:
|
|
case 64:
|
|
deinterleave8bitStride3(DecomposedVectors, TransposedVectors,
|
|
NumSubVecElems);
|
|
break;
|
|
}
|
|
|
|
// Now replace the unoptimized-interleaved-vectors with the
|
|
// transposed-interleaved vectors.
|
|
for (unsigned i = 0, e = Shuffles.size(); i < e; ++i)
|
|
Shuffles[i]->replaceAllUsesWith(TransposedVectors[Indices[i]]);
|
|
|
|
return true;
|
|
}
|
|
|
|
Type *ShuffleEltTy = ShuffleTy->getElementType();
|
|
unsigned NumSubVecElems = ShuffleTy->getNumElements() / Factor;
|
|
|
|
// Lower the interleaved stores:
|
|
// 1. Decompose the interleaved wide shuffle into individual shuffle
|
|
// vectors.
|
|
decompose(Shuffles[0], Factor,
|
|
FixedVectorType::get(ShuffleEltTy, NumSubVecElems),
|
|
DecomposedVectors);
|
|
|
|
// 2. Transpose the interleaved-vectors into vectors of contiguous
|
|
// elements.
|
|
switch (NumSubVecElems) {
|
|
case 4:
|
|
transpose_4x4(DecomposedVectors, TransposedVectors);
|
|
break;
|
|
case 8:
|
|
interleave8bitStride4VF8(DecomposedVectors, TransposedVectors);
|
|
break;
|
|
case 16:
|
|
case 32:
|
|
case 64:
|
|
if (Factor == 4)
|
|
interleave8bitStride4(DecomposedVectors, TransposedVectors,
|
|
NumSubVecElems);
|
|
if (Factor == 3)
|
|
interleave8bitStride3(DecomposedVectors, TransposedVectors,
|
|
NumSubVecElems);
|
|
break;
|
|
default:
|
|
return false;
|
|
}
|
|
|
|
// 3. Concatenate the contiguous-vectors back into a wide vector.
|
|
Value *WideVec = concatenateVectors(Builder, TransposedVectors);
|
|
|
|
// 4. Generate a store instruction for wide-vec.
|
|
StoreInst *SI = cast<StoreInst>(Inst);
|
|
Builder.CreateAlignedStore(WideVec, SI->getPointerOperand(), SI->getAlign());
|
|
|
|
return true;
|
|
}
|
|
|
|
// Lower interleaved load(s) into target specific instructions/
|
|
// intrinsics. Lowering sequence varies depending on the vector-types, factor,
|
|
// number of shuffles and ISA.
|
|
// Currently, lowering is supported for 4x64 bits with Factor = 4 on AVX.
|
|
bool X86TargetLowering::lowerInterleavedLoad(
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LoadInst *LI, ArrayRef<ShuffleVectorInst *> Shuffles,
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ArrayRef<unsigned> Indices, unsigned Factor) const {
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assert(Factor >= 2 && Factor <= getMaxSupportedInterleaveFactor() &&
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"Invalid interleave factor");
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assert(!Shuffles.empty() && "Empty shufflevector input");
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assert(Shuffles.size() == Indices.size() &&
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"Unmatched number of shufflevectors and indices");
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// Create an interleaved access group.
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IRBuilder<> Builder(LI);
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X86InterleavedAccessGroup Grp(LI, Shuffles, Indices, Factor, Subtarget,
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Builder);
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return Grp.isSupported() && Grp.lowerIntoOptimizedSequence();
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}
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bool X86TargetLowering::lowerInterleavedStore(StoreInst *SI,
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ShuffleVectorInst *SVI,
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unsigned Factor) const {
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assert(Factor >= 2 && Factor <= getMaxSupportedInterleaveFactor() &&
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"Invalid interleave factor");
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assert(SVI->getType()->getNumElements() % Factor == 0 &&
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"Invalid interleaved store");
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// Holds the indices of SVI that correspond to the starting index of each
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// interleaved shuffle.
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SmallVector<unsigned, 4> Indices;
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auto Mask = SVI->getShuffleMask();
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for (unsigned i = 0; i < Factor; i++)
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Indices.push_back(Mask[i]);
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ArrayRef<ShuffleVectorInst *> Shuffles = makeArrayRef(SVI);
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// Create an interleaved access group.
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IRBuilder<> Builder(SI);
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X86InterleavedAccessGroup Grp(SI, Shuffles, Indices, Factor, Subtarget,
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Builder);
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return Grp.isSupported() && Grp.lowerIntoOptimizedSequence();
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}
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