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over each node in the worklist prior to combining. This allows the combiner to produce new nodes which need to go back through legalization. This is particularly useful when generating operands to target specific nodes in a post-legalize DAG combine where the operands are significantly easier to express as pre-legalized operations. My immediate use case will be PSHUFB formation where we need to build a constant shuffle mask with a build_vector node. This also refactors the relevant functionality in the legalizer to support this, and updates relevant tests. I've spoken to the R600 folks and these changes look like improvements to them. The avx512 change needs to be investigated, I suspect there is a disagreement between the legalizer and the DAG combiner there, but it seems a minor issue so leaving it to be re-evaluated after this patch. Differential Revision: http://reviews.llvm.org/D4564 llvm-svn: 214020
31 lines
909 B
LLVM
31 lines
909 B
LLVM
; RUN: llc -march=r600 -mcpu=cypress < %s | FileCheck -check-prefix=EG %s
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; EG-LABEL: @and_setcc_setcc_i32
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; EG: AND_INT
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; EG-NEXT: SETE_INT
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define void @and_setcc_setcc_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) {
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%cmp1 = icmp eq i32 %a, -1
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%cmp2 = icmp eq i32 %b, -1
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%and = and i1 %cmp1, %cmp2
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%ext = sext i1 %and to i32
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store i32 %ext, i32 addrspace(1)* %out, align 4
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ret void
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}
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; EG-LABEL: @and_setcc_setcc_v4i32
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; EG: AND_INT
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; EG: AND_INT
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; EG: SETE_INT
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; EG: AND_INT
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; EG: SETE_INT
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; EG: AND_INT
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; EG: SETE_INT
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define void @and_setcc_setcc_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %a, <4 x i32> %b) {
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%cmp1 = icmp eq <4 x i32> %a, <i32 -1, i32 -1, i32 -1, i32 -1>
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%cmp2 = icmp eq <4 x i32> %b, <i32 -1, i32 -1, i32 -1, i32 -1>
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%and = and <4 x i1> %cmp1, %cmp2
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%ext = sext <4 x i1> %and to <4 x i32>
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store <4 x i32> %ext, <4 x i32> addrspace(1)* %out, align 4
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ret void
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}
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