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96 lines
2.7 KiB
LLVM
96 lines
2.7 KiB
LLVM
;; Test that (mul (add x, c1), c2) can be transformed to
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;; (add (mul x, c2), c1*c2) if profitable.
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; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32IM %s
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; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64IM %s
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define signext i32 @add_mul_trans_accept_1(i32 %x) {
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; RV32IM-LABEL: add_mul_trans_accept_1
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; RV32IM: # %bb.0:
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; RV32IM-NEXT: addi a1, zero, 11
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; RV32IM-NEXT: mul a0, a0, a1
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; RV32IM-NEXT: addi a0, a0, 407
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; RV32IM-NEXT: ret
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;
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; RV64IM-LABEL: add_mul_trans_accept_1
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; RV64IM: # %bb.0:
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; RV64IM-NEXT: addi a1, zero, 11
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; RV64IM-NEXT: mul a0, a0, a1
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; RV64IM-NEXT: addiw a0, a0, 407
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; RV64IM-NEXT: ret
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%tmp0 = add i32 %x, 37
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%tmp1 = mul i32 %tmp0, 11
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ret i32 %tmp1
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}
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define signext i32 @add_mul_trans_accept_2(i32 %x) {
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; RV32IM-LABEL: add_mul_trans_accept_2
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; RV32IM: # %bb.0:
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; RV32IM-NEXT: addi a1, zero, 13
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; RV32IM-NEXT: mul a0, a0, a1
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; RV32IM-NEXT: lui a1, 28
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; RV32IM-NEXT: addi a1, a1, 1701
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; RV32IM-NEXT: add a0, a0, a1
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; RV32IM-NEXT: ret
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;
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; RV64IM-LABEL: add_mul_trans_accept_2
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; RV64IM: # %bb.0:
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; RV64IM-NEXT: addi a1, zero, 13
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; RV64IM-NEXT: mul a0, a0, a1
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; RV64IM-NEXT: lui a1, 28
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; RV64IM-NEXT: addiw a1, a1, 1701
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; RV64IM-NEXT: addw a0, a0, a1
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; RV64IM-NEXT: ret
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%tmp0 = add i32 %x, 8953
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%tmp1 = mul i32 %tmp0, 13
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ret i32 %tmp1
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}
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define signext i32 @add_mul_trans_reject_1(i32 %x) {
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; RV32IM-LABEL: add_mul_trans_reject_1
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; RV32IM: # %bb.0:
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; RV32IM-NEXT: addi a1, zero, 19
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; RV32IM-NEXT: mul a0, a0, a1
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; RV32IM-NEXT: lui a1, 9
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; RV32IM-NEXT: addi a1, a1, 585
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; RV32IM-NEXT: add a0, a0, a1
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; RV32IM-NEXT: ret
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;
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; RV64IM-LABEL: add_mul_trans_reject_1
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; RV64IM: # %bb.0:
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; RV64IM-NEXT: addi a1, zero, 19
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; RV64IM-NEXT: mul a0, a0, a1
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; RV64IM-NEXT: lui a1, 9
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; RV64IM-NEXT: addiw a1, a1, 585
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; RV64IM-NEXT: addw a0, a0, a1
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; RV64IM-NEXT: ret
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%tmp0 = add i32 %x, 1971
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%tmp1 = mul i32 %tmp0, 19
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ret i32 %tmp1
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}
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define signext i32 @add_mul_trans_reject_2(i32 %x) {
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; RV32IM: # %bb.0:
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; RV32IM-NEXT: lui a1, 792
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; RV32IM-NEXT: addi a1, a1, -1709
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; RV32IM-NEXT: mul a0, a0, a1
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; RV32IM-NEXT: lui a1, 1014660
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; RV32IM-NEXT: addi a1, a1, -1891
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; RV32IM-NEXT: add a0, a0, a1
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; RV32IM-NEXT: ret
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;
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; RV64IM: # %bb.0:
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; RV64IM-NEXT: lui a1, 792
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; RV64IM-NEXT: addiw a1, a1, -1709
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; RV64IM-NEXT: mul a0, a0, a1
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; RV64IM-NEXT: lui a1, 1014660
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; RV64IM-NEXT: addiw a1, a1, -1891
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; RV64IM-NEXT: addw a0, a0, a1
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; RV64IM-NEXT: ret
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%tmp0 = add i32 %x, 1841231
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%tmp1 = mul i32 %tmp0, 3242323
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ret i32 %tmp1
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}
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