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15879d3807
Add Zbt (ternary) extension code generation to the select lowering tests since it can have a significant impact on how select is lowered. While we are here make the neg-abs commands more consistent with the other tests. Reviewed By: lenary Differential Revision: https://reviews.llvm.org/D94798
164 lines
4.5 KiB
LLVM
164 lines
4.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s --check-prefix=RV32I
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt -verify-machineinstrs < %s \
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; RUN: | FileCheck %s --check-prefix=RV32IBT
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s --check-prefix=RV64I
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; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbt -verify-machineinstrs < %s \
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; RUN: | FileCheck %s --check-prefix=RV64IBT
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declare i32 @llvm.abs.i32(i32, i1 immarg)
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declare i64 @llvm.abs.i64(i64, i1 immarg)
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define i32 @neg_abs32(i32 %x) {
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; RV32I-LABEL: neg_abs32:
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; RV32I: # %bb.0:
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; RV32I-NEXT: srai a1, a0, 31
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; RV32I-NEXT: xor a0, a0, a1
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; RV32I-NEXT: sub a0, a1, a0
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; RV32I-NEXT: ret
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;
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; RV32IBT-LABEL: neg_abs32:
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; RV32IBT: # %bb.0:
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; RV32IBT-NEXT: srai a1, a0, 31
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; RV32IBT-NEXT: xor a0, a0, a1
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; RV32IBT-NEXT: sub a0, a1, a0
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; RV32IBT-NEXT: ret
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;
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; RV64I-LABEL: neg_abs32:
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; RV64I: # %bb.0:
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; RV64I-NEXT: sraiw a1, a0, 31
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; RV64I-NEXT: xor a0, a0, a1
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; RV64I-NEXT: subw a0, a1, a0
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; RV64I-NEXT: ret
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;
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; RV64IBT-LABEL: neg_abs32:
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; RV64IBT: # %bb.0:
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; RV64IBT-NEXT: sraiw a1, a0, 31
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; RV64IBT-NEXT: xor a0, a0, a1
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; RV64IBT-NEXT: subw a0, a1, a0
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; RV64IBT-NEXT: ret
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%abs = tail call i32 @llvm.abs.i32(i32 %x, i1 true)
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%neg = sub nsw i32 0, %abs
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ret i32 %neg
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}
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define i32 @select_neg_abs32(i32 %x) {
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; RV32I-LABEL: select_neg_abs32:
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; RV32I: # %bb.0:
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; RV32I-NEXT: srai a1, a0, 31
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; RV32I-NEXT: xor a0, a0, a1
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; RV32I-NEXT: sub a0, a1, a0
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; RV32I-NEXT: ret
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;
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; RV32IBT-LABEL: select_neg_abs32:
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; RV32IBT: # %bb.0:
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; RV32IBT-NEXT: srai a1, a0, 31
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; RV32IBT-NEXT: xor a0, a0, a1
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; RV32IBT-NEXT: sub a0, a1, a0
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; RV32IBT-NEXT: ret
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;
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; RV64I-LABEL: select_neg_abs32:
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; RV64I: # %bb.0:
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; RV64I-NEXT: sraiw a1, a0, 31
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; RV64I-NEXT: xor a0, a0, a1
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; RV64I-NEXT: subw a0, a1, a0
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; RV64I-NEXT: ret
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;
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; RV64IBT-LABEL: select_neg_abs32:
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; RV64IBT: # %bb.0:
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; RV64IBT-NEXT: sraiw a1, a0, 31
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; RV64IBT-NEXT: xor a0, a0, a1
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; RV64IBT-NEXT: subw a0, a1, a0
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; RV64IBT-NEXT: ret
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%1 = icmp slt i32 %x, 0
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%2 = sub nsw i32 0, %x
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%3 = select i1 %1, i32 %x, i32 %2
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ret i32 %3
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}
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define i64 @neg_abs64(i64 %x) {
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; RV32I-LABEL: neg_abs64:
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; RV32I: # %bb.0:
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; RV32I-NEXT: srai a2, a1, 31
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; RV32I-NEXT: xor a0, a0, a2
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; RV32I-NEXT: sltu a3, a2, a0
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; RV32I-NEXT: xor a1, a1, a2
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; RV32I-NEXT: sub a1, a2, a1
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; RV32I-NEXT: sub a1, a1, a3
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; RV32I-NEXT: sub a0, a2, a0
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; RV32I-NEXT: ret
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;
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; RV32IBT-LABEL: neg_abs64:
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; RV32IBT: # %bb.0:
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; RV32IBT-NEXT: srai a2, a1, 31
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; RV32IBT-NEXT: xor a0, a0, a2
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; RV32IBT-NEXT: sltu a3, a2, a0
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; RV32IBT-NEXT: xor a1, a1, a2
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; RV32IBT-NEXT: sub a1, a2, a1
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; RV32IBT-NEXT: sub a1, a1, a3
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; RV32IBT-NEXT: sub a0, a2, a0
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; RV32IBT-NEXT: ret
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;
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; RV64I-LABEL: neg_abs64:
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; RV64I: # %bb.0:
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; RV64I-NEXT: srai a1, a0, 63
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; RV64I-NEXT: xor a0, a0, a1
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; RV64I-NEXT: sub a0, a1, a0
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; RV64I-NEXT: ret
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;
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; RV64IBT-LABEL: neg_abs64:
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; RV64IBT: # %bb.0:
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; RV64IBT-NEXT: srai a1, a0, 63
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; RV64IBT-NEXT: xor a0, a0, a1
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; RV64IBT-NEXT: sub a0, a1, a0
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; RV64IBT-NEXT: ret
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%abs = tail call i64 @llvm.abs.i64(i64 %x, i1 true)
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%neg = sub nsw i64 0, %abs
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ret i64 %neg
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}
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define i64 @select_neg_abs64(i64 %x) {
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; RV32I-LABEL: select_neg_abs64:
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; RV32I: # %bb.0:
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; RV32I-NEXT: srai a2, a1, 31
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; RV32I-NEXT: xor a0, a0, a2
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; RV32I-NEXT: sltu a3, a2, a0
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; RV32I-NEXT: xor a1, a1, a2
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; RV32I-NEXT: sub a1, a2, a1
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; RV32I-NEXT: sub a1, a1, a3
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; RV32I-NEXT: sub a0, a2, a0
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; RV32I-NEXT: ret
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;
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; RV32IBT-LABEL: select_neg_abs64:
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; RV32IBT: # %bb.0:
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; RV32IBT-NEXT: srai a2, a1, 31
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; RV32IBT-NEXT: xor a0, a0, a2
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; RV32IBT-NEXT: sltu a3, a2, a0
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; RV32IBT-NEXT: xor a1, a1, a2
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; RV32IBT-NEXT: sub a1, a2, a1
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; RV32IBT-NEXT: sub a1, a1, a3
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; RV32IBT-NEXT: sub a0, a2, a0
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; RV32IBT-NEXT: ret
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;
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; RV64I-LABEL: select_neg_abs64:
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; RV64I: # %bb.0:
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; RV64I-NEXT: srai a1, a0, 63
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; RV64I-NEXT: xor a0, a0, a1
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; RV64I-NEXT: sub a0, a1, a0
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; RV64I-NEXT: ret
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;
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; RV64IBT-LABEL: select_neg_abs64:
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; RV64IBT: # %bb.0:
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; RV64IBT-NEXT: srai a1, a0, 63
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; RV64IBT-NEXT: xor a0, a0, a1
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; RV64IBT-NEXT: sub a0, a1, a0
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; RV64IBT-NEXT: ret
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%1 = icmp slt i64 %x, 0
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%2 = sub nsw i64 0, %x
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%3 = select i1 %1, i64 %x, i64 %2
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ret i64 %3
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}
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